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1
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4.8k
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1
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Design a VHDL Code for 4:2 Encoders.
digital system design updated 2.8 years ago by pedsangini276 • 4.8k
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1
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4.4k
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1
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Design a VHDL Code for 2:4 Decoders.
digital system design updated 2.8 years ago by pedsangini276 • 4.8k
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1
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4.4k
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1
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Design a VHDL Code for BCD to 7 Segment Decoder.
digital system design updated 2.8 years ago by pedsangini276 • 4.8k
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1
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14k
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1
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Design a VHDL Code for 4 Bit Ripple Carry Adder.
digital system design updated 2.8 years ago by pedsangini276 • 4.8k
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1
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6.0k
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1
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Design a VHDL Code for 4-Bit Up-Counter.
digital system design updated 2.8 years ago by pedsangini276 • 4.8k
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1
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1.3k
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1
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Write Short note on RAM and SRAM architecture. OR Compare RAM v/s SRAM.
digital system design updated 2.8 years ago by pedsangini276 • 4.8k
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1
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11k
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1
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Write Short note on CPLD and FPGA architecture.
digital system design updated 2.8 years ago by pedsangini276 • 4.8k
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1
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4.0k
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1
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Design Magnitude Comparator using PLAs
digital system design updated 2.8 years ago by pedsangini276 • 4.8k
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1
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11k
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1
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Write Short note on PLA, PAL architecture.
digital system design updated 2.8 years ago by pedsangini276 • 4.8k
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1
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1.3k
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1
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Implement F= (5, 7, 10, 14, 15) and G= (6, 7, 9, 13, 15) Using PLAs.
digital system design updated 2.8 years ago by pedsangini276 • 4.8k
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1
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16k
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1
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Design a VHDL Code for T Flip-Flop.
digital system design updated 2.8 years ago by pedsangini276 • 4.8k
0
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1
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38k
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1
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Write Short note on ROM & RAM architecture.
digital system design updated 2.8 years ago by pedsangini276 • 4.8k
0
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1
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9.7k
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1
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Design a VHDL Code for 4-Bit Down-Counter.
digital system design updated 2.8 years ago by pedsangini276 • 4.8k
0
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1
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2.6k
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1
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Design a VHDL Code for Ring-Counter.
digital system design updated 2.8 years ago by pedsangini276 • 4.8k
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1
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5.5k
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1
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VHDL code for Sequence detector (101) using Moore state machine.
digital system design updated 2.8 years ago by pedsangini276 • 4.8k
1
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1
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9.8k
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1
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VHDL code for Sequence detector (101) using Mealy state machine.
digital system design updated 2.8 years ago by pedsangini276 • 4.8k
0
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1
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2.5k
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1
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Write Short note on CPLD
digital system design updated 2.8 years ago by teamques10 ★ 68k
0
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1
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1.3k
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1
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Eliminate redundant states & draw reduced state diagram
digital system design updated 2.8 years ago by sagarkolekar ★ 11k
0
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1
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12k
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1
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Write a VHDL Code for JK Flip-Flop.
digital system design updated 2.9 years ago by sagarkolekar ★ 11k
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1
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1.4k
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1
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Explain what is Entity in VHDL is.
digital system design updated 2.9 years ago by teamques10 ★ 68k
1
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1
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2.2k
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1
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Compose VHDL code for implementation of D Flip-Flop.
digital system design updated 2.9 years ago by pedsangini276 • 4.8k
0
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1
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464
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1
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What is shift refister? Explain any one type of shift register. Give its application.
digital system design updated 3.5 years ago by teamques10 ★ 68k
0
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1
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415
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1
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Compare combinational circuit with sequential circuit
digital system design updated 3.5 years ago by teamques10 ★ 68k
0
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1
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649
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1
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Explain 3:8 decoder
digital system design updated 3.5 years ago by teamques10 ★ 68k
1
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1
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10k
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1
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Implement the following Boolean function with 8: multiplexer F(A,B,C,D)=?m(0,3,5,6,8,9,10,12,14).
digital system design updated 3.5 years ago by teamques10 ★ 68k
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