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Digital Logic Design

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State and prove De Morgan's theorem.
digital logic design updated 3.1 years ago by Sharad • 160
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105k
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Design 4-bit binary to gray code conversion OR Design and implement 4 bit binary to gray code converter
digital logic design updated 3.2 years ago by teamques10 ★ 69k
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State truth table of 3 bit Gray to Binary conversion then design it using 3:8 decoder and additional gates.
digital logic design updated 3.6 years ago by teamques10 ★ 69k
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VHDL program format ?
digital logic design updated 4.1 years ago by ninadsail • 10
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1.4k
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Write short notes on about operators in VHLD
digital logic design updated 4.1 years ago by ninadsail • 10
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2.1k
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Write short note on VHDL features.?
digital logic design updated 4.1 years ago by ninadsail • 10
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1.1k
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Write a VHDL Program for NAND gate?
digital logic design updated 4.1 years ago by ninadsail • 10
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10.0k
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Write VHDL Program for NAND gate.?
digital logic design updated 4.1 years ago by ninadsail • 10
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901
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Design VHLD Program EX-OR gate?
digital logic design updated 4.1 years ago by ninadsail • 10
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1.0k
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Write VHDL program for Subtractor?
digital logic design updated 4.1 years ago by ninadsail • 10
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1.1k
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What are advantages of VHDL. Write VHDL program for full adder.
digital logic design updated 4.1 years ago by ninadsail • 10
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1.1k
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Explain Entity in VHLD and write VHDL program for half subtractor cricuit
digital logic design updated 4.1 years ago by ninadsail • 10
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1.9k
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Design a half adder using VHDL
digital logic design updated 4.1 years ago by ninadsail • 10
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11k
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Draw the diagram of a 4 bit twisted ring counter. Explain its operation with the help of a timing diagram
digital logic design updated 4.1 years ago by ninadsail • 10
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Draw the diagram of a 4 bit twisted Johnson Counter ,explaining its operation with the help of a timing diagram.
digital logic design updated 4.1 years ago by ninadsail • 10
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Design 4 bit synchronous up counter using T flip flop
digital logic design updated 4.1 years ago by ninadsail • 10
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2.9k
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Design a synchronous counter which goes through following states using J-K flip flop 1-3-5-7-1 (10m)
digital logic design updated 4.1 years ago by ninadsail • 10
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Design a synchronous counter which goes through following states using J-K flip flop 0-2-4-6-0 (10m)
digital logic design updated 4.1 years ago by ninadsail • 10
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3.0k
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Design a module-9 up counter using 4 bit ripple counter
digital logic design updated 4.1 years ago by ninadsail • 10
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37k
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Design mod -3 up counter using J-k flip flop
digital logic design updated 4.1 years ago by ninadsail • 10
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5.7k
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Explain working of universal shift register?
digital logic design updated 4.1 years ago by teamques10 ★ 69k
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4.2k
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With neat diagram and explain 4 bit bidirectional shift register
digital logic design updated 4.1 years ago by teamques10 ★ 69k
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2.2k
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what is race condition ? why does it occur.
digital logic design updated 4.1 years ago by ninadsail • 10
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3.9k
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Working of T Flip Flop
digital logic design updated 4.1 years ago by teamques10 ★ 69k
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1.7k
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Convert JK flip flop to D flip flop (4m)
digital logic design updated 4.1 years ago by ninadsail • 10
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