1.Cache is a small but fast memory device that the CPU can access at relatively faster speeds and that holds a subset of the data in the main memory. They store information the CPU is most likely to need next. If the data item is present in the cache, it is termed as a cache hit otherwise it is a cache miss. A typical organization is shown in Figure 10.

2.The same reason we have a memory hierarchy prompts us to have multi-level caches as well.A cache miss, on the other hand, means the CPU has to go scampering off to find the data elsewhere. This is where the L2 cache comes into play — while it’s slower, it’s also much larger. If data can’t be found in the L2 cache, the CPU continues down the chain to L3 and so on.

3.L1 caches are designed to be the fastest as they are closest to the CPU and thus it will be accessed typically by the CPU and the access time of L1 cache has a major effect on the clock rate of the CPU.L1 caches are normally much smaller than the other levels of cache but is much bigger than the CPU’s registers.L1 cache is normally on chip with processor as shown in the diagram.

4.However recent processors are also known to have multiple levels of cache on the processor chip. Since the processor chip needs to be of a certain size, this highly limits the size of on chip cache. Thus external cache levels are also fairly common.L1 is the smallest in size and gives fastest access.

5.L2 on the other hand is relatively slower but is bigger in size giving higher hit rates. L3 is slower as far as the access time is considered (not as slow as the main memory) and even bigger when the size is considered. This continues for all the cache levels.

6.Some processors use an inclusive cache design (meaning data stored in the L1 cache is also duplicated in the L2 cache) while others have an exclusive cache design (meaning the two caches never share data).

7.The access time of the caches also depends on whether the caches are on chip with the processor or are external to the processor.

8.If u consider a three level cache memory having L1, L2 and L3, the average access time (t) is given by

$t= h_1C_1 + (1- h_1) h_2 C_2+ (1- h_1) (1- h_2) C_3+ (1- h_1) (1- h_2) (1- h_3) M$

h1=Hit rate in L1

h2 = Hit rate in L2

h3 = Hit rate in L3

C1= Access Time of L1

C2= Access Time of L2

C3= Access Time of L3

M=Access Time of Main memory

The number of misses in the L2 and L3 cache given be the terms $(1- h_1) (1- h_2) \ \ and \ \ (1- h_1) (1- h_2) (1- h_3)$ should be as low as possible. This is the reason why L2 and L3 are larger to get higher hit rates and lower miss rates, resulting in very few main memory accesses.