Solution:

Very - Long - Instruction -Word (VL|W) processing is an essential approach for substantially increasing the number of instructions processed per cycle.

A Very - long -instruction - Word is essentially a concentration of several short instructions and requires multiple execution units, running in parallel, to carry out the instruction in a single cycle.

5 The principles of VLIW architecture s data flow for the TMS320C $62 \times$ family of advanced fixed point DSP processor is shown in the figure.

The CPU contains two data paths and eight independent execution units, organized into two sets,

$L_1, S_1, M_1$ and $D_1 \&$ $L_2, S_2, M_2$ and $D_2$

In this case, each short instruction is 32 bits wide and eight of these are linked together to form a very long instruction packet that may be executed in parallel.

The VLIW processing starts when the CPU fetches an instruction packet from the on-chip program memory.

The eight instructions in the fetch packet are formed into an execute packet if they can be executed in parallel, and then dispatch to the eight execution units as appropriate.

The next 256-bit instruction packet is fetched from the program memory while the execute packet is decoded and executed.

If the eight instructions were all multiplied in a fetch packet and are not executable in parallel then several execute packets will be formed and dispatched to the execution units one at a time.

A fetch packet is always 256 bits wide but an execute packet may vary between one and eight instructions - The VLIW architecture is designed to support instruction-level parallels.

This architecture with fast clock speeds.

lead to a very high-performance DSP processor.

However, the computational efficiency of such processors fails if the instructions cannot be executed in parallel.