Mumbai University > ELECTRO > Sem 3 > Digital Circuits and Designs

Marks: 7M

Year: May 2014 , Dec 2014

JTAG:

• The Joint Test Action Group (JTAG) is an electronics industry association formed in 1985 for developing a method of verifying designs and testing printed circuit boards after manufacture.

• The Boundary-scan method (also known as JTAG boundary-scan) is a method of testing modern Printed Circuit Boards (PCBs) after assembly. Using the dedicated test logic built into many of today’s integrated circuits (ICs), boundary-scan checks if each device is correctly inserted and soldered onto the PCB.

• Typical devices that incorporate boundary-scan technology include CPLDs, FPGAs, microprocessors, DSPs, ASICs, bus logic, etc. A number of device manufacturers embracing boundary-scan technology are Intel, Analog Devices, ARM, Freescale, NXP, PLX, ST, TI, Renesas, Xilinx, Altera, Lattice, Broadcom and Actel among others.

• A JTAG interface is a special interface added to a chip. Depending on the version of JTAG, two, four, or five pins are added. Boundary-scan enabled devices feature dedicated test access port (TAP) signals: TCK (Test Clock), TMS (Test Mode Select), TDI (Test Data In), TDO (Test Data Out). TRST (Test Logic Reset) (optional)

• A test probe need only connect to a single "JTAG port" to have access to all chips on a circuit board. To simplify the test infrastructure within a PCB it is common to connect the devices in a serial (daisy chain) formation so that the first device's TDO connects to the next device’s TDI (and so on) to form a so-called scan chain.

• JTAG boundary scan technology provides access to many logic signals of a complex integrated circuit, including the device pins. The signals are represented in the boundary scan register (BSR) accessible via the TAP. This permits testing as well as controlling the states of the signals for testing and debugging. Therefore, both software and hardware (manufacturing) faults may be located and an operating device may be monitored.

• When combined with built-in self-test (BIST), the JTAG scan chain enables a low overhead, embedded solution to testing an IC for certain static faults (shorts, opens, and logic errors). The scan chain mechanism does not generally help diagnose or test for timing, temperature or other dynamic operational errors that may occur. Test cases are often provided in standardized formats such as SVF, or its binary sibling XSVF, and used in production tests. The ability to perform such testing on finished boards is an essential part of Design For Test in today's products, increasing the number of faults that can be found before products ship to customers.

BIST:

• Modern day ICs based on deep sub-micron technology may develop failures after initial fault checking and even during operation within expected life time.

• To cater to this problem sometimes redundant circuitry are kept on-chip which replace the faulty parts. To enable replacement of faulty circuitry, the ICs are tested before each time they startup. If a fault is found, a part of the circuit (having the fault) is replaced with a corresponding redundant circuit part (by re-adjusting connections). Testing a circuit every time before they startup, is called Built-In-Self-Test (BIST).

• BIST is basically same as off-line testing using ATE where the test pattern generator and the test response Analyzer are on-chip circuitry (instead of equipment). As equipment are replaced by circuitry, so it is obvious that compressed implementations of test pattern generator and response Analyzer are to be designed.