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Write a VHDL description of Logic Gates.
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Solution:

VHDL description of Logic Gates:

Hardware description languages (HDLs) differ from software programming languages because HDLs include ways of describing logic connections and characteristics.

  • An HDL implements a logic design in hardware (PLD), whereas a software programming language, such as C or BASIC, instructs existing hardware what to do.

  • The two standard HDLs used for programming PLDs are VHDL and Verilog. Both of these HDLs have their advocates, but VHDL will be used in this textbook.

  • Shows VHDL programs for gates described in this VHDL description. Two gates are left as Checkup exercises. VHDL has an entity/architecture structure.

  • The entity defines the logic element and its inputs/outputs or ports; the architecture describes the logic operation. Keywords that are part of the VHDL syntax are shown bold for clarity.

(a) OR gate:

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  • entity OR gate is,

  • port (A, B: in bit; X: out bit);

  • end entity OR gate;

  • architecture OR function of OR gate is,

  • begin

  • X 6= A OR B;

  • end architecture OR function;

(b) AND gate:

enter image description here

  • entity AND gate is,

  • port (A, B: in bit; X: out bit);

  • end entity AND gate;

  • architecture AND function of AND gate is,

  • begin

  • X 6= A AND B;

end architecture AND function;

(c) NAND gate:

enter image description here

  • entity NAND gate is,

  • port (A, B, C: in bit; X: out bit);

  • end entity NAND gate;

  • architecture NAND function of NAND gate is,

  • begin

  • X 6= A NAND B NAND C;

  • end architecture NAND function;

(d) XNOR gate:

enter image description here

  • entity XNOR gate is,

  • port (A, B: in bit; X: out bit);

  • end entity XNOR gate;

  • architecture XNOR function of XNOR gate is,

  • begin

  • X 6= A XNOR B;

  • end architecture XNOR function;

(e) NOT gate:

enter image description here

  • entity Inverter is,

  • port (A: in bit; X: out bit);

  • end entity Inverter;

  • architecture NOT function of Inverter is

  • begin

  • X 6= NOT A;

  • end architecture NOT function;

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