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written 8.8 years ago by gravatar for teamques10 teamques10 ★ 69k •   modified 8.8 years ago

Mumbai University > COMPS > Sem 3 > Digital Logic Design and Analysis

Marks: 5 M

Year: Dec 2013
digital logic design
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written 8.8 years ago by gravatar for teamques10 teamques10 ★ 69k

1) Logic Diagram:

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2) Timing Diagram:

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3) Working:

  • Assume initially Q0,Q1,Q2,Q3=0001. As soon as first clock pulse is applied, as per nature of D F/F the output follows the input. Therefore Q0Q1Q2Q3=1000.

  • After the second clock pulse $Q_0 Q_1 Q_2 …

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