Interface two 16K X 8 EPROMS and two 32K X 8 RAM chips with 8086. select suitable maps.

Interface between two 16K X 8 EPROMS and two 32K X 8 RAM chips with 8086

• The last address on the map of 8086 is FFFFFH.

• After resetting, the processor starts from FFFF0H.

• Hence this address must lie in the address range of EPROM.

• The figure below shows the interfacing diagram, and the table below shows a complete map of the system:

• It is better not to use a decoder to implement the above map because it is not continuous, i.e. there is some unused address space between the last RAM address (0FFFFH) and the first EPROM address (F8000 H).

• Hence the logic is implemented using logic gates as shown in the below figure: