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Design full adder using 3:8 decoder with active low outputs and NAND gates.
written 8.5 years ago by gravatar for teamques10 teamques10 ★ 69k •   modified 8.5 years ago

Mumbai University > COMPS > Sem 3 > Digital Logic Design and Analysis

Marks: 5 M

Year: Dec 2013
digital logic design
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written 8.5 years ago by gravatar for teamques10 teamques10 ★ 69k •   modified 8.5 years ago

1.Block Diagram:

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2.Truth Table:

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3.Expression for Sum (S): $S(A, B, C_{IN}) = \sum m(1,2,4,7)$

4.Expression for Carry $(C_{OUT})$: $C_{OUT}(A, B, C_{IN}) = \sum m (3,5,6,7)$

5.Logical circuit:

enter image description here
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