1) Transfer Characteristic:

The transfer characteristic can be deduced by applying a slowly ramping input voltage and determining the sequence of events which takes place with respect to changes in the states of conduction of each transistor and the critical points at which the onset of these changes happen. Consider the circuit input vs. output transfer characteristic curve shown in figure below.

1. Break Point P1:

• With the input near 0 volts and the base current supplied to $Q_1$, this transistor can conduct in the forward mode. Since the only source of collector current is the leakage of $Q_2 , Q_1$ will be driven into saturation. This ensures that $Q_2$ is off which, in turn, means that Q$_3$ is off. While there is no load present, there are leakage currents flowing in the output stage which allow the transistor $Q_4$ and the diode $D_1$ to be barely conducting in the ON state.

  $V_{OUT} = V_{CC} - V_{BE4} - V_{D1} \\ V_{OUT} = 5 - 0.6 - 0.6 = 3.8V \\ Point \ \ P1: V_{IN} = 0.5, V_{OUT} = 3.8V$

1. Break Point P2:

2. As the input voltage is slightly increased, the above state continues until, with $Q_1$ on and in saturation, the voltage at the base of $Q_2$ rises to the point of conduction. Then:

   $V_{IN} = V_{BE2} - V_{CE1(SAT)} = 0.6 - 0.1 = 0.5 \\ Point \ \ P2: V_{IN} = 0.5, V_{OUT} = 3.8V$

3. Break Point P3:

4. As the input voltage is further increased, $Q_2$ becomes more conducting, turning fully ON. Base current to $Q_2$ is supplied by the now forward biased base-collector junction of $Q_1$ which is still in saturation. Eventually, $Q_3$ reaches the point of conduction. This happens when:

   $V_{IN} = V_{BE2} + V_{BE3} - V_{CE1(SAT)} \\ V_{IN} = 0.7 + 0.6 - 0.1 = 1.2V$

5. Note that with transistor $Q_3$ just at turn on, $V_{BE3} = 0.6V$ which means that the current through $R_3$ is $0.6V/470Ω = 1.27mA$. With operation in the linear active region, the collector current in $Q_2$ is $0.97 × 1.27mA = 1.23mA. ˜ a_F I_{E2}$
6. The voltage drop across $R_2$ is then $V_{R2} = 1.23mA × 2.2 kΩ = 2.7V$.

7. Under this condition the collector to emitter voltage drop across $Q_2$ is:

   $V_{CE2} = V_{CC} - V_{R2} - V_{R3} \\ V_{CE2} = 5 - 2.7 - 0.6 = 1.7V$

8. This confirms that $Q_2$ is still operating in the forward active mode.

9. With $Q_3$ beginning to conduct there is a conduction path for current through $Q_4$ and the diode, $D_1$, which then turns fully ON. In this case: $V_O = V_{CC} - V_{R1} - V_{BE4} - V_{D1} \\ V_O = 5 - 0.94 - 0.65 - 0.6 = 2.81V \\ Point \ \ 3: V_i = 1.2V, VO = 2.81V$

10. Break Point P4:

11. As the input voltage is further increased, $Q_2$ conducts more heavily, eventually saturating. $Q_3$ also conducts more heavily and eventually reaches the point of saturation also. As $Q_2$ becomes more conducting, its collector current increases. This in turn increases the voltage drop across R1 which in turn means that the voltage across $Q_2$ i.e. $V_{CE2}$ drops. This falls below the requirement for conduction in $Q_4$ and the diode, $D_1$, so that both of these turn OFF prior to the saturation of $Q_3$.

12. When $Q_3$ reaches the edge of saturation:

    $V_i = V_{BE2} + V_{BE3} - V_{CE1} \\ V_i = 0.7 + 0.7 - 0.1 = 1.5V \\ Point \ \ 4: Vi = 1.4V, V_O = 0.2V$

2) Fan-in:

Fan-in is the number of inputs a gate can handle. Physical logic gates with a large fan-in tend to be slower than those with a small fan-in.

3) Fan-Out:

It is the greatest number of inputs of gates of the same type to which the output can be safely connected. The maximum fan-out of an output measures its load driving capability.