A complementary CMOS inverter is implemented as the series connection of a p-device and an n-device, as shown in the Figure above. The source and the substrate (body) of the p -device is tied to the VDD rail, while the source and the substrate of the n-device are connected to the ground bus. Thus, the devices do not suffer from anybody effect. To derive the DC transfer characteristics for the CMOS inverter, which depicts the variation of the output voltage $(V_{out})$ as a function of the input voltage $(V_{in})$, one can identify five following regions of operation for the n -transistor and p -transistor.

Region 1: This region is defined by 0 < $V_{in}$ < $V_{tn}$, which means that the input voltage is low, lower than threshold voltage of nmos. Thus in this region, the n-device is cut off, and the p-device is in the linear region. The drain-to-source current for the p-device is also zero. So the nmos acts as an open switch and pmos as a closed switch, connecting the output node to the $V_{DD}$. Thus for $V_{in}$ = 0, the output voltage is high, $V_{out}$ = $V_{DD}$.

Region 2: This region is characterized by an input voltage greater than the threshold voltage of nmos device, ie $V_{tn} =\lt V_{in} \lt V_{DD}/2$ in which the p-device is in its non-saturated region while the n-device is in saturation. The VTC curve just enters the transition region, where the slope of curve is -1.

Region 3: This region in the centre of the VTC curve is characterized by input voltage near $V_{DD}/2$, called the transition or unstable region. In this region both the n- and p-devices are in saturation. The output voltage is undefined in this region, hence it is avoided in an inverter. This is represented by two current sources in series. From the transfer curve, it may be seen that the transition between the two states is very step. This characteristic is very desirable because the noise immunity is maximized.

Region 4: This region is described by input voltage lower than the threshold voltage of pmos device, $V_{DD}/2 \ltV_{in} =\lt V_{DD} + Vtp$. The p-device is in saturation while the n-device is operation in its non-saturated region. The output voltage goes low in this region after the second slope of -1 on the VTC curve.

Region 5: This region is defined by the input condition $V_{in} \gt= V_{DD}-Vtp$, in which the p-device is cut off, and the n-device is in the linear mode. Thus, the pmos acts as a open switch while nmos acts as a closed switch, connecting the output to the ground. Hence output in this region is $V_{out}$ = 0.