Logic Design - Jun 2013

Computer Science Engg. (Semester 3)

TOTAL MARKS: 100
TOTAL TIME: 3 HOURS (1) Question 1 is compulsory.
(2) Attempt any four from the remaining questions.
(3) Assume data wherever required.
(4) Figures to the right indicate full marks. 1 (a) Write the truth table of the logic circuit having 3 inputs, A, B and C and the output expressed as Y=ABC+ABC. Also simplify the expression using Boolean algebra and implement the logic circuit using NAND gates.(6 marks) 1 (b) Name universal gates. Realize basic gates using NAND gates.(8 marks) 1 (c) Explain positive and negative logic.(6 marks) 2 (a) Give sum-of-product of sum circuit for.
f(A, B, C, D)=∑m(6,8,9,10,11,12,13,14,15)(8 marks) 2 (b) Find essential prime implicants for the Boolean expression by using Quine-McClunky method.
f(W,X,Y,Z)=∑(1,3,6,7,8,9,10,12,13,14)(12 marks) 3 (a) Design a 16 to 1 multiplexer using two 8 to 1 multiplexer and one 2-to-1 multiplexer.(6 marks) 3 (b) Explain n-bit magnitude comparator.(8 marks) 3 (c) Design 7-segments decoder using PLA.(6 marks) 4 (a) Explain Schimmit trigger.(6 marks) 4 (b) Give state transition diagram of SR, D, JK and T FlipFlops.(8 marks) 4 (c) Show how a D Flip-Flop can be converted into JK-Flip Flop.(6 marks) 5 (a) Design 3-bit PISO (Use D -FlipFLop).(6 marks) 5 (b) Design two 4-bit serial adder.(6 marks) 5 (c) Design 4-bit Johnson counter with state table.(8 marks) 6 (a) Design Synchronous mod 6 up-counter using JK - Flip Flop.(10 marks) 6 (b) Explain digital clock with block diagram.(10 marks) 7 (a) Reduce state transition diagram (Moore model) Fig.Q7(a) given below by,
(i) Row elimination method and
(ii) Implication table method, with partition table. (12 marks) 7 (b) Design an asynchronous sequential logic circuit for state transition diagram shown below Fig.Q7(b). (8 marks) 8 (a) Explain with logic diagram 3-bit simultaneous A/D converters.(10 marks) 8 (b) Explain with neat diagram, single-slope A/D converter.(10 marks)