Basic Electronics - Jun 2013

First Year Engineering (C Cycle) (Semester 1)

TOTAL MARKS: 100
TOTAL TIME: 3 HOURS (1) Question 1 is compulsory.
(2) Attempt any four from the remaining questions.
(3) Assume data wherever required.
(4) Figures to the right indicate full marks.

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1 (a) (i) When forward-biased, a diode
a) blocks current
b) conducts current
c) has a high resistance
d)drops a large voltage(1 marks) 1 (a) (ii) The knee voltage of a Silicon diode is:
a) 0.3V
b) 0.5V
c) 0.7V
d) None of these(1 marks) 1 (a) (iii) The ripple factor of half wave rectifier is about?
a) 40.6
b) 0.46
c) 1.21
d) 81.2(1 marks) 1 (a) (iv) The RMS value of a load current in case of a full wave rectifier is:
a) ?/2
b) I_m/2
c) I_m/?2
d) I_m/?(1 marks) 1 (b) Deduce the following for HWR.
i) I_rms
ii) I_DC(4 marks) 1 (c) With a neat circuit diagram, explain the working principles of a full wave bridge rectifier.(6 marks) 1 (d) Draw the circuit of full wave rectifier and show that the ripple factor=0.48 and efficiency=81%.(6 marks)

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2 (a) (i) The current relationship between two current gain in a transistor is:
a) ?=?/(1-?)
b) ?=(1+?)/(1-?)
c) ?=(1-?)/(1+?)
d) ?=(?+1)/?(1 marks) 2 (a) (ii) The ?_DC of a transistor is its:
a) current gain
b) voltage gain
c) power gain
d) internal resistance(1 marks) 2 (a) (iii) In a transistor the current conduction is due to _____ carriers.
a) Majority
b) Minority
c) Both A&B
d) None of these(1 marks) 2 (a) (iv) In a transistor circuit:
a) I_E = I_C
b) I_E > I_C
c) I_E < I_C
d) I_E << I_C(1 marks) 2 (b) Draw input and output characteristics of an NPN transistor in common base configuration and explain.(8 marks) 2 (c) Calculate the value of I_C, I_E and ?_DC for a transistor with ?=0.99 and I_B=110�A.(4 marks) 2 (d) Obtain the relationship between '?_DC' and '?_DC'.(4 marks)

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3 (a) (i) The intersection of a DC load line and the output characteristics of a transistor is called:
a) Q-Point
b) Quiescent point
c) Operating point
d) All of these(1 marks) 3 (a) (ii) For an emitter follower, the voltage gain is:
a) Unity
b) Greater than unity
c) Less than unity
d) Zero(1 marks) 3 (a) (iii) The best biasing stability is achieved by using _____ biasing circuit.
a) Fixed
b) Collector to base
c) Voltage divider
d) None of these(1 marks) 3 (a) (iv) In self bias or emitter bias ciruit _____ is connected between emitter and ground.
a) Inductor
b) Transformer
c) Resistor
d) Capacitor(1 marks) 3 (b) Explain the concept of base bias techniques using NPN transistor.(10 marks) 3 (c) Calculate the Q-point values for the circuit of collector to base circuit. Given R_B=100k?, R_C=10k?, V_cc=12V and ?_DC=100.(6 marks)

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4 (a) (i) SCR has _____ number of layers.
a) One
b) Two
c) Three
d) Four(1 marks) 4 (a) (ii) The minimum point in VI characteristic of UJT is known as _____ point.
a) Negative
b) Valley
c) Latching
d) Conducting(1 marks) 4 (a) (iii) The FET is a _____ controlled device.
a) Current
b) Voltage
c) Power
d) None of these(1 marks) 4 (a) (iv) The relaxation oscillator uses:
a) MOSFET
b) SCR
c) BJT
d) UJT(1 marks) 4 (b) Draw the two transistor equivalent circuit of SCR. Also plot V-I characteristics and explain various regions of operations.(10 marks) 4 (c) Explain with suitable diagram and waveform how UJT can be used as a relaxation oscillator.(6 marks)

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5 (a) (i) Oscillator uses _____ type of feedback.
a) Positive
b) Negative
c) Both A&B
d) None of these(1 marks) 5 (a) (ii) A phase shift oscillator has:
a) Three RC circuits
b) Three LC circuits
c) T-type circuit
d) ?-type circuit(1 marks) 5 (a) (iii) The frequency of a Hartley oscillator is f= _____
a) 1/2??(LC)
b) 1/2??(RC)
c) 1/2??C
d) 1/2?LC(1 marks) 5 (a) (iv) The upper and lower critical frequencies are sometimes called the
a) Power frequencies
b) Half power frequencies
c) 6 dB points
d) None of these(1 marks) 5 (b) Explain with a neat diagram, the working of a single stage RC couple amplifiers with its frequency response.(8 marks) 5 (c) Give any four advantages of negative feedback in an amplifier.(4 marks) 5 (d) In a Colpitt's oscillator, if the desired frequency is 800 kHz, determine values of L and C_eq if C₁=C₂=10pF.(4 marks)

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6 (a) (i) The CMRR is given by _____
a) A_d×A_c
b) A_c / A_d
c) A_d / A_c
d) 20 log A_c / A_d(1 marks) 6 (a) (ii) The gain of the inverting amplifier using R_f=10k? and R₁= 1k? is _____
a) -10
b) -11
c) 10
d) 11(1 marks) 6 (a) (iii) The gain of voltage follower is _____
a) Zero
b) Infinite
c)Negative
d) Unity(1 marks) 6 (a) (iv) The screen of CRT is coated with:
a) Chromium
b) Phosphor
c) Carbon
d) Germanium(1 marks) 6 (b) Calculate the output voltage of a three input summing amplifier:
Given
R₁=200k?
R₂=250k?
R₃=500k?
R_f=1M?
V₁=-2V
V₂=2V
V₃=1V.(6 marks) 6 (c) Show how an op-amp can be used as an integrator. Derive an expression for output voltage.(6 marks) 6 (d) Give any four applications of CRO.(4 marks)

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7 (a) (i) The modulating frequency is _____ carrier frequency.
a) lower than
b) higher than
c) equal to
d) none of these(1 marks) 7 (a) (ii) The modulation is done in _____
a) Transmitter
b) Receiver
c) None of the above
d)Between transmitter and receiver(1 marks) 7 (a) (iii) The 2's complement of 1010 gives:
a) 1111
b) 0110
c) 0010
d) 0101(1 marks) 7 (a) (iv) In binary numbers, shifting the binary point one place to the right:
a) divides by 2
b) decreases by 10
c) increases by 10
d) multiplies by 2(1 marks) 7 (b) With suitable block diagram explain function of super heterodyne receiver.(8 marks) 7 (c) Convert (ABCD)₁₆=( )₂=( )₈=( )₁₀=( )_BCD(4 marks) 7 (d) Subtract (28)₁₀-(19)₁₀ using both 1's complement and 2's complement methods.(4 marks)

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8 (a) (i) When deMorgan's theorem is applied to (A+B)', we get _____
a) A+B
b) A'B'
c) A
d) B(1 marks) 8 (a) (ii) Y=A'B+B'A is a Boolean expression for:
a) EX-OR
b) EX-NAND
c) EX-NOR
d) None of these(1 marks) 8 (a) (iii) The example for universal gate is _____
a) NOT
b) NOR
c) OR
d) AND(1 marks) 8 (a) (iv) The expression for half adder carry 'C' with inputs 'A' and 'B' is given by:
a) A+B
b) AB
c) A'B'
d) None of these(1 marks) 8 (b) i) Realize the NAND gate using minimum number of NOR gates.
ii) Simplify M=XYZ + XY'Z+ Z'XY and realize using NOR gates.(8 marks) 8 (c) Realize a full adder using two half adders and an OR gate with truth table.(8 marks)