nFET logic:

Once the nFET logic is designed, it can be used in a variety of circuits. The figure below shows three possibilities. The structure if fig. a represents standard complementary structuring where we create a pFET array using bubble pushing to obtain the series-parallel pFET array. The static pseudo-nMOS approach in fig. b could be used, but we would have to be concerned about device ratios to insure that the output low voltage  is sufficiently small without using excessively large nFETs. This is avoided if we opt for a dynamic logic family as in fig. c. This, however, introduces timing problems and gives outputs that are only valid for a short period of time. Obviously, the selection of the circuit family involves considering many factors.

We can use multiple-output domino logic (MODL) as a basis. This is possible because the nesting of the carry bits from one bit to the next gives the ANDing relationship needed to implement MODL. To see this analytically, we have

We can use c1 as one output, and c2 as another output with the two related by the AND operation. Since this type of relationship is valid for c3 and c4, only a single MODL gate is needed to produce all four carry bits.