The ARM processor supports seven operating modes. The processor mode decides availability of the registers to the programmer and also access rights to the CPSR.

The processor modes are classified as :

1. Privileged mode
2. Non-privileged mode.

Privileged mode supports full read and write access to the CPSR. The privileged modes supported by processor core are :

1. Abort
2. Fast interrupt request
3. Interrupt request
4. Supervisor
5. Undefined
6. System.

Non-privileged mode allows only read access to the control field in the CPSR. However it allows read-write access to the condition flags. Non-privileged mode supported by processor core is :

1. User mode
   • It is a non privileged mode. Most of the tasks are executed in the user mode.
   • Memory access is restricted in user mode. User cannot read directly from hardware device.
2. Fast Interrupt Mode (FIQ  mode)
   • This mode is entered whenever a high priority of interrupt is raised
   • FIQ mode is used to handle the peripherals that issue fast interrupts.
   • This mode is privileged mode. The devices causing FIQs are floppy disc handling data, serial port etc.
3. Interrupt Mode (IRQ)
   • This mode is a privileged mode.
   • It is entered when a low priority interrupt is raised. e.g. keyboard, hard disk, floppy disc etc

Difference between FIQ and IRQ

• An IRQ may be interrupted by an FIQ but an FIQ cannot be interrupted by IRQ.
• With FIQ we have to do processing fast. For achieving this, the processor has shadow registers.
• FIQs cannot call software interrupts (SWIs).
• If it becomes essential for an FIQ routine to re-enable interrupts, it will take longer time than it would take by an IRQ.
• FIQ should disable interrupts.

1. Supervisor mode (SVC)
   • The ARM processor enters this mode on rest. This mode can also be entered if a software interrupt (SWI) instruction is executed.
   • Supervisor mode has additional privileges that allow greater control of the system.
   • An operating system kernel operates in this mode.
   • In order to read from a I/O Module, programmer has to enter the supervisor mode.
2. Abort mode
   • The abort mode is entered whenever an attempt access memory fails.
3. Undefined mode (Undef)
   • This mode is use to handle undefined instructions.
4. System mode
   • This mode is a privileged mode. It is a special version of the user mode.
   • It allows full read-write access to the CPSR.
   • It is present in ARM architecture version 4 and above.

The instructions used to transfer from ARM7 mode to THUMB mode are listed below:

1. The usual way to enter Thumb mode is 'bx rN' command with LSB of rN set to '1'. If the LSB of the "rN" is '0', the processor will switch to ARM mode.
2. There is also 'blx' command. If the least significant bit of the target address is a one, the processor will switch to Thumb mode. Similarly, if the bit is a zero, the processor will switch to ARM mode.