The ARM architecture supports two program status registers. They are the current program status register (CPSR) and the saved program status register (SPSR).

The CPSR is accessible in all the processor modes while the SPSR is accessible in privileged modes.

The CPSR contains condition code flags, interrupt disable bits, current processor mode and other control and status information.

Each exception mode contains a saved program status register (SPSR). It is responsible for holding the value of CPSR in case the exception occurs.

Fig. shows the format of the CPSR and SPSR registers:

Now let us see description of each bit.

Control Bits (Bits 0-7)

Bits (0-7) are the control bits of CPSR and SPSR register. These bits change incase an exception occurs. The control bits can be altered by the software only when the processor is in privilege mode.

Bits 0-4 (Processor Mode)

These bits determine the processor mode. The modes are listed in Table

Bit 5 (Thumb Bit) (Architecture version 4T only)

The Thumb bit determines the state of the ARM core. The state of core determines the instruction set that is being executed.

Bits 6, 7 (Interrupt Masks)

The ARM core has two interrupts. They are fast interrupt request (FIQ) and interrupt request (IRQ). These interrupts are maskable. Bit 6 (F) controls the FIQ and Bit 7 (I) controls the IRQ. For their mask enable/disable. When bit is set i.e. F = 1 or I = 1 the respective interrupt is masked or disabled. When bit is clear, the interrupt is unmasked or available.

Condition code flags

The flags are updated by the operations performed by the ALU. The flags in the CPSR can be tested by the instructions to determine whether the instruction is to be executed or not. The flags can be updated by execution of a comparison instruction or by execution of arithmetic, logical or move instruction where the destination register is not R15.

Bit 27 (Saturation Flag : Q)

It is present on the DSP extension of ARM processor core. This bit is set if an overflow or saturation occurs. The hardware can only set this flag. In order to clear this bit we need to write to CPSR directly. In case of SPSR this bit is used to hold and restore the CPSR Q flag incase of exceptions.

Bit 28 (Overflow Flag : V)

This flag is set if an overflow occurs while addition or subtraction. For operations other than addition/subtraction overflow is unchanged.

Bit 29 (Carry Flag : C)

This flag is set if one of the following conditions exist.

1. For addition alongwith the comparison instruction CMP, if the addition produced a carry otherwise flag is clear.
2. For subtraction alongwith the comparison instruction CMN, if subtraction produced a borrow, then the carry flag is cleared otherwise it is set.
3. For operations not involved with addition/subtraction but include a shift operation, the carry flag is set to the last bit shifted out of the value by the shifter. For operations that do not include a shift, carry flag remains unaltered.

Bit 30 (Zero flag : Z)

If the result of comparison is zero i.e. equal numbers are present then the zero flag is set to 1. Z flag is otherwise cleared.

Bit 31 (Negative Flag : N)

The negative flag is set if the result is negative and regarded as two’s complement of a signed integer. Otherwise the flag is cleared if the result is positive or zero.

Other methods to modify the N, Z, C and V flags are listed below :

1. Execution of flag setting variants arithmetic and logical instructions such that the destination register is R15. The variants also copy the SPSR to CPSR. They are mainly used while returning from exceptions.
2. Execution of MRC instruction such that the destination register is R15.
3. Execution of MSR instruction, as part of its function of writing a new value to CPSR or SPSR.
4. Execution of some variants of LDM instruction.

Reserved bits

These bits are reserved for further expansion in future. The user should write his program in such manner that the bits are unmodified. If the user fails to do this it may lead to side-effects on future versions of the architecture.