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Comparison of RISC and CISC
Properties | RISC | CISC |
---|---|---|
Number of Instructions | Less | More |
--- | --- | --- |
Addressing Modes | Less | More |
Instruction Formats | Less | More |
Instruction Size | Fixed | Variable |
Control Unit | Hardwired | Micro-programmed |
Number of Bus Cycles to execute an instruction | Single CPU cycle (for 80% Instructions) | Multiple CPU cycles |
Control Logic And Decoding Subsystem | Simple | Complex |
Pipelining | Huge no. of stages of Pipelining | Difficulty in efficient implementation |
Design time and Probability of Design Errors | Smaller time and less probable | Long time and Significant probability |
Complexity of Compiler | Simpler | More complex and the results of “optimization” may not be most efficient and the fastest machine language code |
HLL instructions | Supported | Not Supported |
ARM Microcontroller Core
ARM is the industry’s leading provider of 32-bit embedded RISC microprocessors with almost 75% of the market. ARM offers a wide range of processor cores based on a common architecture and delivering high performance together with low power consumption and system cost.
The ARM processor range provides solutions for :
- Open platforms running complex operating systems for wireless, consumer and imaging applications.
- Embedded real-time systems for mass storage, automotive, industrial and networking applications.
- Secure applications including smart cards and SIMs.
The ARM architecture incorporated a number of features from RISC design like:
A load-store architecture
- A load-store architecture means that ALU instructions cannot access memory, they can operate only on registers. Data transfer between memory and processor is possible only by Load and Store instructions.
- LOAD instruction is used to load the data from memory into the processor’s register.
- STORE instruction is used to store data in memory from the processor’s register.
- The data in the registers can be processed by the ALU.
Fixed-length 32-bit instructions
- All the instructions are 32-bit in length.
- This fixed length instructions make the design of the control unit simpler.
- Fixed length instructions also make it possible to use Hardwired control unit, which makes the operation of control unit faster.
3-address instruction formats
- This is also referred to as 3-opeand instructions
- The two source operands are different than the destination operand for e.g. in the add instruction given below
- ADDd, s1, s2 ; Operation of above instruction:d := s1 + s2
f bits | n bits | n bits | n bits |
---|---|---|---|
function | Op 1 addr. | Op 2 addr. | Dest. Addr. |
Fig.: A 3-address instruction format.
Simplicity:
The combination of the simple hardware with an instruction set that is grounded in RISC ideas but retains a few key CISC features, and thereby achieves a significantly better code density than a pure RISC, has given the ARM its power-efficiency and its small core size. This simplicity gives
- A high instruction throughput
- An excellent real time interrupt response
- A small and cost effective processor
SOC:
A SOC may be embedded with the following components:
- Embedded processor that may be General Purpose Processor (GPP) or Application Specific Instruction set Processor (ASIP)
- Single purpose processing core or multiple processor cores
- A network bus protocol implementing core
- An encryption unit
- Signal processing unit
- Field Programmable Gate Array (FPGA) to implement some logical circuit
- Memory
- Analog units
One of the widely used place for SOC is mobile phones. Single purpose processors are configured for dialing, modulating, demodulating, deciphering, interfacing keypad and multi line LCD or graphic LCD, touch screen, storing data.