The ARM processor uses a nomenclature that describes the processor implementations.

The word "ARM" is followed by letters and numbers indicating features of the processor as given below:

ARM {x}{y}{z}{T}{D} {M}{I}{E}{J} {F}{S}

Such that

Hence, for ARM7TDMI

• It implies that processor core is based on ARM7 family.
• It supports the Thumb instruction set.
• It supports debug via JTAG interface.
• It supports the long multiply instructions.
• It supports hardware breakpoints and watchpoints via the Embedded ICE macrocell.

The Thumb instruction set is supported for all versions after version 4. The variant T is automatic for ARM v6 and above.

The core supports debug via JTAG interface. JTAG interface is described by IEEE 1149.1 standard Test Access Port and boundary scan architecture. It is used to send and receive debug information between processor core and the test equipment. The variant D is automatic for ARM v5 and above.

The ARM core supports long multiply instructions for version 3 and above.

Embedded ICE macrocell is the debug hardware that is built in processor for setting breakpoints and watchpoints.

Enhanced DSP instructions are included in version 5 and above of ARM architecture. Variant E is included for all versions of ARM v6 and above.

The ARM core supports Jazelle Java acceleration architecture.

It also supports vector floating point architecture.

Synthesizable version implies that the processor core is supplied as source code that can be compiled  into form easily used by EDA tools.