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Differentiate between RISC and CISC processors.
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Properties RISC CISC
Number  of Instructions Less More
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Addressing Modes Less More
Instruction Formats Less More
Instruction Size Fixed Variable
Control Unit Hardwired Micro-programmed
Number of Bus Cycles to execute an instruction Single CPU cycle (for 80% Instructions) Multiple CPU cycles
Control Logic And Decoding Subsystem Simple Complex
Pipelining Huge no. of stages of Pipelining Difficulty in efficient implementation
Design time and Probability of Design Errors Smaller time and less probable Long time and Significant probability
Complexity of Compiler Simpler More complex and the results of “optimization” may not be most efficient and the fastest machine language code
HLL instructions Supported Not Supported
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