Designing reliable CMOS chips involve careful circuit design and processing with attention directly to the following potential reliability problems:

• Hot electron effect
• Electro migration.
• Oxide failure
• Bipolar transistor degradation
• Package/chip power dissipation
• ESD protection
• On chip noise and cross talk
• Power and ground bouncing
• single event upset
• Latch-up in CMOS I/O and internal circuits

Currently chips are subjected to a process called accelerated life testing where packaged chips are subjected to overvoltage and over temperature in an effort to emulate the aging process. Any failures may then be used to estimate the actual lifetime of the part. This process is time consuming and comes right at the end of the project.

Usually the wafer lots with poor yields also cause reliability problems. For eg. When a particular wafer processing is poorly controlled, thus causing aluminium over etching, many chips on the wafer may suffer from open-circuited metallic interconnects. Some chips with severely over etched, but not fully open circuited interconnects may pass the test. But under current stress, such interconnects can be open-circuited because of electromigration problem, causing chip and system failures in the field. Any good manufacturing practice should weed out such potential failures during the accelerated reliability test.

Currently, research 48, 49 attempts to build simulators that can estimate the reliability of a chip at the earliest possible point in the design cycle. These simulators are sure to be increasingly used as designers aim to increase the reliability of their chips and systems.