The various clock generation techniques are as follows:

Inverter based clock generation circuit

Basic approach involves using cascaded inverters to produce ф and фbar

1. We have to design clock generator in such a way that delay times t1 (delay through the chain of first row 3 inverters) and t2 (delay through the chain of second row 2 inverters) are equal.
2. Design is based on equalizing electrical effort when C1 and C2 are unequal
3. Skew problem is minimized by carefully sizing each inverter.
4. Thus by using the concept of LOGICAL EFFORT delays t1 and t2 of upper and lower path are made same.

Clock generation using D latch:

Another technique for generating two clock phases uses D latch.

In an SR latch with complemented inputs, the output are always complemented and thus can be used to get ф and фbar.

H-tree architecture:

Even  a moderately complex design has several thousands of clock driven transistors. To simplify the routing closely spaced points are grouped together and the problem reduces to driving GROUPS and SUPER groups (those groups which consist of smaller groups).

This is basically bottom-top approach that is followed wherein first individual receiver points are tackled up-to the clock generator. Once the basis of the problem is recognized a TOP-DOWN approach can be used.

Thus any clock distribution scheme is designed first by geometrically defining clocking groups and receiver points. After this is done the cells are fit into the floor plan to match the optimal design .

One such distribution geometry is theH-architecture.

This technique is based on the shape of the letter H and the symmetry of the letter shows that the distance of the point X from any tip A (lXA) is constant. If the signal is broadcast at X and the receivers are at equivalent points A then the delay is given by;

A master clock is placed a point X and the received signals are taken from the tips of small Hs . these points can be used a sources for local distribution of clock signals.H-tree seems to be an obvious solution for the problem of clock distribution but following points must be remembered

• The lengths and electrical characteristics must be same for each clock path to achieve the desired effect.
• Load capacitances at the receiver point must be the same.

A constraint of the H-architecture is that it requires a lot of planning at the circuit and physical design levels and this may not be practical.

Stabilization:

Clock is applied externally to a chip. There should be some management technique inside the chip to synchronize its operation with the external clock. This is called Clock Stabilization.

Basic approach for clock stabilization is as follows

Clock generator produces necessary clock. It is fed to delay line which slows it own (if necessary), depending upon Vadj. The output signal is sampled and sent to a phase detector circuit where it is compared with external clock. Phase detector produces an output which indicates if the output signal is leading or lagging the external clock. This information is used by the low pass filter which produces a corresponding voltage Vadj, that controls the RC time constant of the delay line circuit

The improved version of the above scheme is by using PLL. PLL detects any phase difference between External clock and output clock generation and tries to minimize it.