As technology is advancing majorly due to device minimization, the wire interconnects starts playing a vital role in determining performance of the system. As the device dimensions are scaled down, so are the dimensions of wires scaling down. The minimum width of the wire is scaled by factor S. Thus wire capacitance scales down by a factor of 1/S.

For global interconnects such as the long wires used route VDD and ground, The RC delay must be as minimum as possible. The wire resistance (for global interconnect) dominates the resistance of the driving logic gate and it increases with each new technology generation. Thus to minimize increase in global interconnect delay, the cross sectional area of global interconnects is not scaled. i.e. W and H are not scaled down for global interconnects.