DRAM cell using 1 transistor:

A 1-transistor DRAM cell is as shown in figure. It consists of a single access nFET Mn and a strong capacitor Cs. The cell is controlled by the word line signal WL and a single bit provides the I/O path to the cell.

The storage mechanism is based on the concept of temporary charge retention on the capacitor. A voltage Vs across the capacitor corresponds to a stored charge Qs of

With Qs=0 C and Vs = 0V, the charge state is logic 0.

Conversely, a large value of Vs gives large Qs, which is defined as a logic 1, charge state.

Write operation: Write operation is as follows:

Applying VDD to the nFET gate turns ON the access transistor and allows the access to storage capacitor. The input data voltage Vd controls the current to/from Cs and the capacitor charges or discharges depending on state of Vd. In case if Vd=VDD, the largest voltage that can be passed to the capacitor is

This gives a maximum charge of,

The hold state is achieved by turning OFF the access transistor with a word line signal of Vpower=0. And the hold time ‘th’ is defined as the longest period of time that the cell can maintain a large voltage to be interpreted as logic 1.

Read operation: The voltage Vs on the capacitor at the read provides the voltage to make the charge Cs to the bitline capacitance which sets up charge sharing situation.

The initial charge on the capacitor is,

where Vs=0V for logic 0and Vs>0 for logic 1. The current flows from Cs to bit and continues until the voltages are equal to a final voltage,

The initial and final charges are same so we have,

Refreshing mechanism: The hold time for SRAM cell is in the order of few μsec. Thus, charge leakage problem could violate the data after hold time. To avoid this problem, DRAM employs a refresh mechanism where the data is periodically read from every cell. Amplified and then rewritten.