Electro Static Discharge protection is located at the pads to prevent an overshoot in voltage caused by any reason to breakdown a transistor especially if it is at the gate of a MOSFET, whose oxide thickness is too small in the deep submicron technologies. ESD in its simplest form can be regarded as a diode which bypasses large spikes.

Input Circuit:

There are several sources of ESD. Charged objects near or touching IC pins can discharge through on-chip devices. Thus input protection networks are used to protect the circuit from getting destroyed due to ESD. As a protection, the input pads are not directly connected to the gate of the MOS transistor, instead an ESD protection circuit is added between the input PAD and the MOSFET gate. These networks are included so as to provide an alternate charge flow path to keep excessive charge levels always away from the gate of transistor.

Diodes can be used with resistors to form input protection circuit as shown below -

If an excessively large positive voltage is applied to the input pad, the resistors drop the voltage level along the input line. Under these conditions, the diodes D1 and D2 undergo breakdown and steer charge away from the gates of the input stage transistors. The diodes in a CMOS circuit typically have VZ=10-12V or smaller depending upon the junction.

To prevent the circuit from ESD effects, the ICs are designed with circuit to protect the input of transistor from excessive charge levels. The input protection circuits are designed to provide an alternate path for charge to discharge during ESD event. The protection circuit comes into the picture only during the situation when voltage at the input pins goes beyond the normal voltage range; otherwise it should not have any effect on the circuit during the normal operation mode.

Another input protection scheme is as shown in the above figure. This uses diodes D1 and D2 but additional diodes D3 and D4 have been added between the input and the power supply. The circuit keeps the DC voltage reaching the gate in the range [–Vd,VDD-Vd ]  where Vd≈0.7V is the on-voltage of the diode i.e the value required to induce current flow. A special high-threshold voltage nFET has been included to provide additional charge drainage. This uses the thick isolation field oxide (FOX) as a gate insulator so that the weak field-effect gives a high threshold voltage VTF that is typically around 10-15 V. Under normal operating conditions VPTF and i=0. If a high input voltage increases VP to a valueVTF, the FET turns on and i flows, keeping charge away from the logic gate input.

Output circuit:

One of the important parts of the high speed chip is the output driving circuit. The output driver circuits are useful in increasing the current driving capability so that the charging and discharging of the capacitor seen at the output pad is faster. On chip speed are increasing at greater pace with the improvement in the technology. However, if the output circuitry is not designed to drive the larger capacitive loads, then all of the speed of the internal logic has no meaning.

There are several approaches to fulfil this requirement such as:

1. Driver chain
2. Tristate circuits
3. BICMOS