Pipelining is technique that is used to increase the throughput of a sequential set of distinct data inputs through a synchronous logic cascade. Since computer instructions are inherently sequential in nature, pipelining is used in microprocessors to increase the million instructions per second rating. Pipelined systems are designed to increase the overall throughput of a set of sequential input states by dividing the cascade into smaller sections and using a faster system clock. Figure provides a visualization of the problem. The input registers feed several complex logic chains, each having a characteristic delay time Td, the chain with the largest value of td determines the clock rate for this unit; the numerical value of the delay time for a logic cascade is established by the circuit design style, the processing parameters and the physical design.

The idea of pipelining can be understood by noting that logic calculations start at the input sections and propagate through the chain to the output. Once a circuit completes a calculation and passes a result to the next stage, it remains idle for the rest of the clock cycle. The progression of the clock occurs at the time when t=0. Succesive times are denoted by t1 where ti+1 >t1 for t=1, 2, 3. Since the delay through a logic gate varies its complexity and parasitic, the logic propagation rate will not be uniform. Some circuits will exhibit longer delays than others. This is the basic for pipelining.

If we divide the long logic into smaller groups add registers between the sections and use a faster clock then most of the circuits will be active at a given time. Fig shows 4-stage pipeline. Each stage consists of a set of input registers and a logic network. The clock frequency fpipe=1/tpipe is set by the slowest stage and is larger than the frequency used in the original cascade; however pipeline design does not itself give a faster response. For a 4-stage one, the total time delay will be 4tpipe as compared to the original clock period T in the non-pipelined network. If the CMOS technology used for both the designs are same then the 4tpipe can be made greater than T. The advantage of such a kind of system is that it increases the rate of output results. For example, let the number of sequential inputs be N. In non pipelined design, it takes a total of NT second to produce all the results. A pipeline on the other hand produces a output every in conjunction with every clock cycle once it is completely filled for the active length of the pipeline e.g. for 4-stage one, the time needed to produce all the results is 4tpipe + (N-1) tpipe=(N+3) tpipe

Where the term on the left side denotes the time required to initially fill the pipe this is an idealized value and assumes that it is possible to maintain a full pipeline.

Advantages of Pipelining:

1. The cycle time of the processor is reduced, thus increasing instruction issue-rate in most cases.
2. Some combinational circuits such as adders or multipliers can be made faster by adding more circuitry. If pipelining is used instead, it can save circuitry vs. a more complex combinational circuit.

Disadvantages of Pipelining:

1. A non-pipelined processor executes only a single instruction at a time. This prevents branch delays (in effect, every branch is delayed) and problems with serial instructions being executed concurrently. Consequently the design is simpler and cheaper to manufacture.
2. The instruction latency in a non-pipelined processor is slightly lower than in a pipelined equivalent. This is due to the fact that extra Flipflops must be added to the data path of a pipelined processor.
3. A non-pipelined processor will have a stable instruction bandwidth. The performance of a pipelined processor is much harder to predict and may vary more widely between different programs.