The switching speed of CMOS gate is limited by the time taken to charge and discharge the load capacitance CL. An input transition results in an output transition that either changes CL towards VDD or discharges CL towards VSS. The switching performance of CMOS circuit is determined by the speed at which gate can operate, the speed is measured in terms of Rise time, Fall time and Propagation delay.

RISE TIME(tr):

It is a time taken for a waveform to rise from 10% to 90% of its steady state value.

FALL TIME(tf):

It is time taken for a waveform to fall from 90% to 10% of its steady state value.

DELAY TIME(td):

It is a time difference between the input transition (50%) and the 50% output transition.

Fall time:

From the switching characteristics, it is evident that the fall time tf consists of two intervals

1. tf1 = period during which the capacitor voltage Vout drops from 0.9VDD to (VDD - Vtn).
2. tf2 = period during which the capacitor voltage Vout drops from (VDD – Vtn) to 0.1VDD.

Thus, integrating while in saturation,

CL (dVout/dt) + (Bn/2) (VDD-Vtn)2 = 0

where,

(Bn/2)(VDD-Vtn)2=current through the NMOS when it is in saturation.

Integrating from t = t1 corresponding to Vout=0.9VDD to t = t2 corresponding to Vout=(VDD-Vtn).

Hence, we obtain,

tf1 = 2Cl(Vtn - 0.1VDD) / Bn(VDD - Vtn)2

Similarly, when the NMOS is in linear region, time tf2 is taken to discharge the capacitor voltage from (VDD – Vtn) to 0.1VDD can be obtained as before giving,

tf2 = Cl ln(19 -20n) / Bn VDD(1-n)

Adding tf1 and tf2 …

Finally,

tf = tf1 + tf2

Hence we obtain tf as,

tf = (2Cl / Bn VDD (1-n)) [ ((n - 0.1)/(1-n)) +(1/2 ln(19 - 20n))]

Fall time tf is approximated as,

tf = (k*Cl) / Bn VDD

k is approximated as 2 to 5 for VDD from 1.8 to 5 volts.

Rise Time:

Due to symmetry of CMOS circuits, a similar approach may be used to obtain rise time tr.

tr = (2 Cl / BpVDD(1-p))[(p-0.1)/(1-p) + ½ ln (19-20p)]

where,

p = |Vtp| / VDD

tr = 3 à 4 Cl / BpVDD

For equally sized NMOS and PMOS transistors, Bn = 2Bp

Hence, tf = tr / 2

The fall time is faster than the rise time due to different carrier mobilites associated with P and N device (un = 2up)

If we need same rise and fall time for an inverter, Bn / Bp = 1

Hence, channel width for the PMOS device should be increased to approximate 2 to 3 times that of N device.

Wp = 2 to 3 times Wn

Delay Time:

In most CMOS circuits the delay of a single gate is dominated by output rise and fall time.

tdr = tr / 2

tdf =  tf / 2

Average delay for rising and falling transitions,

tavg = (tdf + tdr) / 2

Thus, from the above equations for Rise time, Fall time and Delay time, we get

trise = k Cl / BpVDD

tfall = k Cl / BnVDD

where, k is approximated as 2 to 5, for a VDD from 1.8 to 5 volts.

Hence, k is approximately equal to 2.2, for VDD = 1.8 volt.

Parameters affecting the switching performance of CMOS circuits are:

1. Load capacitance (Cl)
2. Supply voltage (VDD)
3. Device transconductance
4. Input waveform slope

Methods to improve switching performance of CMOS circuits:

Load Capacitance

The delay is directly proportional to the load capacitance; to achieve high speed the load capacitance should be minimized. Hence there is limitation of fanout, hence the circuit can drive fewer transistors.

Supply Voltage

The delay is inversely proportional to supply voltage, thus if VDD is increased delay time is reduced and lowering VDD reduces the speed of gate.

Static power dissipation is given as,

Pstatic = VDD Id

Dynamic power dissipation is given as,

Pdynamic = Cl (VDD2) f

An increase in VDD causes an increase in power dissipation.

Device Transconductance

The delay is inversely proportional to device transconductance, which in turn depends on device aspect ratio, thus delay can be reduced by increasing aspect ratio. However this implies that more area on chip is consumed which decreases the number of devices that can be placed on the die area.

Input Waveform Slope

Input waveform slope modifies gate delay ,if input rises or falls rapidly the delay in output is reduced ,thus input waveform slope must be high for better switching performance.