Sample and Hold Circuit :

A sample and hold circuit samples an input signal and holds on to its last sampled value until the input is sampled again. Figure 1 shows the circuit diagram of sample and hold circuit :

The performance parameter of sample and hold amplifier circuits are as follows :

1) Sampling Pedestal or hold step :

This occurs each time it goes from sample mode to hold mode and there is always a small error in the voltage being held that makes it different from the input voltage at the time of sampling. This error should be small and even more importantly be signal independent to avoid nonlinear distortion.

2) Another measure is called droop rate in hold mode, which characterizes a slow change in output voltage in hold mode.

3) Signal feedthrough is a measure of how isolated is the sampled signal from input signal during hold mode. Ideally, output voltage will no longer be affected by changes in the input voltage. In reality, there is always some signal feedthrough, usually through parasitic capacitance coupling from the input to the output. This signal feedthrough can be minimized.

4) Speed :

When Op-Amps are used, its 3dB bandwidth and slew rate should be maximized for high speed operation at the price of power consumption.

5) Aperture jitter or uncertainty, which is a result of effective sampling time changing from cycle to cycle. When high-speed input signals are sampled, it causes the held voltage to be significantly different from the ideal held voltage.