1. A master-slave flip-flop is normally constructed from two flip-flops: one is the Master flip-flop and the other is the Slave. In addition to these two flip-flops, the circuit also includes an inverter.
2. The inverter is connected to clock pulse in such a way that the inverted CP is given to the slave flip-flop. For example, if the Clock Pulse =0 for a master flip-flop, then the output of the inverter is 1, and this value is assigned to the slave flip-flop. In other words if Clock Pulse=0 for a master flip-flop, then Clock Pulse =1 for a slave flip-flop.
3. Master Slave JK flip flop is a combination of clock JK & clock SR latch.
4. JK latch acts as Master and SR latch acts as slave.
5. Master is positive level edge triggered and the slave will respond to negative level.
6. During the positive half of the clock the master is active and a negative half cycle , slave is active.

DIAGRAM:

WORKING:

Case I:

For clock = 1, master is active, slave is inactive. J = K =0.

Therefore, output of master will not change. Hence S and R inputs to the slave will remain unchanged.

As soon as clock = 0 slave becomes active and master is inactive and since S nd R inputs are not changed slave outputs will also remain unchanged. J=K=0

Case II:

Clock = positive edge triggered. J=K=0

Operation will be same as above.

Case III:

Clock = positive edge triggered. J=0 , K=1

Clock = 1 – Master active, Slave inactive.

Output of master $Q_1 = 0 \ and \ Q_1= 1$

Therefore, S = 0 , R = 1

Clock = 0 –Slave active ,Master inactive.

Output of Slave $Q =0 \ and \ \bar Q = 1$

Again if clock = 1, Master active, Slave inactive.

Even with changed outputs fed back to Master outputs $Q_1=0 \ and \ \bar Q_1 =1$

Therefore S = 0 and R = 1

Even when clock = 0 slave becomes active again, outputs of slave remain unchanged. Therefore we get stable output from Master and Slave.

Case IV:

Clock = 1- Master active, Slave inactive

Outputs of Master $ Q_1 =1 \ and \ \bar Q_1 =0.$

Therefore  S=1 R=0

Clock = 0- Master inactive slave active

Outputs of slave $Q=1 \ and \ \bar Q_1 =0$

Case V:

Clock = 1: Master active Slave inactive

Outputs of Master will toggle. Hence S, R are inverted.

Clock =0: Master inactive Slave active

Outputs of Slave will toggle.

These changed outputs are returned back to Master inputs

Since clock=0 master is inactive and won’t respond.

This avoids the multiple toggling thereby avoiding race around condition.

TRUTH TABLE:

Master Slave JK flip flop –

The Master-Slave Flip-Flop is basically a combination of two JK flip-flops connected together in a series configuration. Out of these, one acts as the “master” and the other as a “slave”. The output from the master flip flop is connected to the two inputs of the slave flip flop whose output is fed back to inputs of the master flip flop.

In addition to these two flip-flops, the circuit also includes an inverter. The inverter is connected to clock pulse in such a way that the inverted clock pulse is given to the slave flip-flop. In other words if CP=0 for a master flip-flop, then CP=1 for a slave flip-flop and if CP=1 for master flip flop then it becomes 0 for slave flip flop.

Working of a master slave flip flop –

1.When the clock pulse goes to 1, the slave is isolated; J and K inputs may affect the state of the system. The slave flip-flop is isolated until the CP goes to 0. When the CP goes back to 0, information is passed from the master flip-flop to the slave and output is obtained.

2.Firstly the master flip flop is positive level triggered and the slave flip flop is negative level triggered, so the master responds before the slave.

3.If J=0 and K=1, the high Q’ output of the master goes to the K input of the slave and the clock forces the slave to reset, thus the slave copies the master.

4.If J=1 and K=0, the high Q output of the master goes to the J input of the slave and the Negative transition of the clock sets the slave, copying the master.

5.If J=1 and K=1, it toggles on the positive transition of the clock and thus the slave toggles on the negative transition of the clock.

6.If J=0 and K=0, the flip flop is disabled and Q remains unchanged.

Timing Diagram of a Master flip flop –

1.When the Clock pulse is high the output of master is high and remains high till the clock is low because the state is stored.

2.Now the output of master becomes low when the clock pulse becomes high again and remains low until the clock becomes high again.

3.Thus toggling takes place for a clock cycle.

4.When the clock pulse is high, the master is operational but not the slave thus the output of the slave remains low till the clock remains high.

5.When the clock is low, the slave becomes operational and remains high until the clock again becomes low.

6.Toggling takes place during the whole process since the output is changing once in a cycle.

This makes the Master-Slave J-K flip flop a Synchronous device as it only passes data with the timing of the clock signal.