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Design a full adder using two 4:1 mux
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written 3.6 years ago by | modified 2.9 years ago by |
To implement a ful adder using $4\times 1$ multiplexer first we will draw the truth table of a full adder.
Inputs | Outputs | |||
---|---|---|---|---|
A | B | Cin | S | Cout |
0 | 0 | 0 | 0 | 0 |
0 | 0 | 1 | 1 | 0 |
0 | 1 | 0 | 1 | 0 |
0 | 1 | 1 | 0 | 1 |
1 | 0 | 0 | 1 | 0 |
1 | 0 | 1 | 0 | 1 |
1 | 1 | 0 | 0 | 1 |
1 | 1 | 1 | 1 | 1 |
We are getting two outputs Sum (S) and Carry (Cout).
The boolean function of S and Cout can be written as,
$S=\Sigma m (1,2,4,7)\\[2ex]C_{out}=\Sigma m(3,5,6,7)$
Since $4\times 1$ mux is to be used, it will have only one input and two selection lines.
Here we use $A$ as an input nd $B, C$ as selection lines. The two $4\times 1$ mux are cascaded. * The input$A$ and$\bar{A}$ are connected to lines I0, I1, I2 and I3 respectively of$4\times 1$ mux for sum. * The inpuut logic '0',$A$,$\bar{A}$ and logic '1' are connected to inputs of I4, I5, I6 and I7 respectively of$4\times 1$ mux for Cout.
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