The salient features of CMOS logic family are:

1. Logic voltage levels:

CMOS devices operating under normal conditions are guaranted to produce output voltage levels within well defined LOW and HIGH ranges.

1. DC Noise margin:

It is the maximum noise voltage added to an input signal of a digital circuit that doesn't cause an undesirable change in the circuit output.

1. Fanout:

The number of inputs that the gate can drive without exceeding its worst case loading specifications. The fanout depends not only on the characteristics of the output but also on the inputs that it is driving.

1. Power dissipation:

• The power dissipation represent power dissipated per logic gates
• It is measured in mW

$P_{diss}=V_{cc} \ \ \ I_{c \ avg}\\ I_{c \ avg}=\dfrac {I_{C_{on}}+I_{C_{off}}}{2}$

1. Propogation Delay:

• It is measured in nano seconds.
• The amount of time taken for change in the input signal to produce a change in the output signal.
• Several factors lead to non zero propogation delay.
• It is measured at the midpoint of transitions

tpHL=The time between an input change and the corresponding output change when the output is changing from High to Low.

tpLH=The time between an input change and the corresponding change when the output is changing from Low to High.