Block Diagram of internet Architecture of XC 9500 Family CPLD

Architectural Description:

• The Xilinx XC 9500 series is a family of CPLD with varying number of external input | output pins and internal PLDs.
• Each External i|o pin can be used as an input,an output or a bidirectional pin according to device programming.
• Any of the 3 pins at the bottom can be used as 'Global Clocks'(GCK).
• Each macro cell can be programmed to use a selected clock input.
• One pin can be used as a 'Global set/reset (GSR).
• Each macro cell can use this signal as an asynchronous Preset or Clear.
• 2 or 4 pins depending on the devices can be used as 'Global Three State Controls (GTS).
• One of the signals can be selected in each macrocell's output is hooked to an external i|o pin.
• The internal PLDs in Xilinx are called as function blocks (FBs)
• Each internal PLD has 36 inputs and 18 macrocells and outputs. Hence, it can be called as a "36v18"
• Only four functional blocks (FB) are shown but XC 9500 scales to accomodate 16 FBs in the XC 95288.
• Regardless tp the specific family member each FB programmable receives 36 signals from the switch matrix.
• The inputs to the Switch matrix are the 18 macro cell outputs from each of the functional blocks and the external inputs from the i|o pins.

Function Block:

• The Functional Block consists of 18 independent macro cells capable of implementing combinational or a registered function.
• Functional Block also receives global clock, outputs enable, set/reset signals.
• The functional block generates 18 outputs that drive Fast, Connect switch matrix.
• These 18 outputs and their corresponding 18 o|p enable signals also drive the i|o block.
• 36 inputs provides 72 true and complement signals into programmable AND-array to form 90 product terms.
• Product term allocator allocates any number of these 90 product terms on each macrocell.
• Each function block supports local feedback paths that allow any number of functional outputs to drive its own programmable AND array without going outside the Functional Block.

Macrocells:

• Each macrocell of XC9500 is capable of getting configured to implement a combinatorial or registerd function.
• It is possible to configure the macrocell register as a D-type or T-type flip flop or we can bypass it for the combinatorila operation.
• The global clock and set /reset signals are available to all macro cells.
• It consists of:

1. Switch Matrix: The switch matrix combines multiple internal connections into a