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Write a VHDL code for full adder.
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written 3.6 years ago by
teamques10
★ 69k
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Full adder using behavioural description in VHDL,
library IEEE;
use IEEE.STD_LOGIC-1164.ALL;
entity fulladder is
port (a, b, ci: in std_logic; sum, co: out std_logic);
end fulladder;
entity fa of fulladder is
begin
process(ci)
begin
if (ci == 0)
sum <= a xor b;
co <= a and b;
else
sum <= a xnor b;
co <= a or b;
end if;
end process:
end fa;
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