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Design a 4:1 multiplexer using only NAND gates.
1 Answer
written 3.6 years ago by |
S0 | S1 | Output |
---|---|---|
0 | 0 | A0 |
0 | 1 | A1 |
1 | 0 | A2 |
1 | 1 | A3 |
Output = S0'.S1' + S0'.S1 + S0.S1'+ S0.S1
For 2 inputs X and Y
X OR Y= NOT[ NOT( X AND X ) AND NOT( Y AND Y )]
X AND Y= NOT[ NOT( X AND Y ) AND NOT( X AND Y ) ]