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What are different biasing techniques used to bias D-MOSFET and E-MOSFET. Explain with the help of appropriate circuit diagrams.
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  • The junction gate field-effect transistor (JFET or JUGFET) is the simplest type of field-effect transistor.
  • They are three-terminal semiconductor devices that can be used as electronically-controlled switches, amplifiers, or voltage-controlled resistors.Unlike bipolar transistors,
  • JFETs are exclusively voltage-controlled in that they do not need a biasing current. Electric charge flows through a semiconducting channel between source and drain terminals.
  • By applying a reverse bias voltage to a gate terminal, the channel is "pinched", so that the electric current is impeded or switched off completely.
  • A JFET is usually on when there is no potential difference between its gate and source terminals.
  • If a potential difference of the proper polarity is applied between its gate and source terminals, the JFET will be more resistive to current flow, which means less current would flow in the channel between the source and drain terminals.
  • Thus, JFETs are sometimes referred to as depletion-mode devices.

DIFFERENT METHODS OF BIASING IN JFET:

The general relationships that can be applied to the dc analysis of all FET amplifiers

IG=0;ID=IS

JFET & D-MOSFET, Shockley's equation is applied to relate the input & output quantities:

ID=IDSS(1VGSVP)2

For E-Type MOSFETs

ID=k(VGSVT)2

FIXED BIAS CONFIGURATION:

The Drain Source voltage euation by applying KVL is given by

VDS=VDDIDRD

We know that for when source voltage is zero that is

VS=0V

VC=VDS

V=VGS

VGS=VGG

SELF BIAS CONFIGURATION:

The controlling gate-to-source voltage is now determined by the voltage across a resistor RS introduced in the source leg of the configuration 

The current through RS is the source current IS but IS = ID and

VRS=IDRS

By applying KVL at Gate Source junction we have

VGSVRS=0andVGS=IDRS

Substituting into Shockleys equation we have

ID=IDSS[1VGSVp]2

ID=IDSS[1+IDRSVp]2

Applying KVL to the output circuit to determine the VDS

VRS+VDS+VRDVDD=0

but ID=IS

VDS=VDDID(RS+RD)

We know that VG=0 and VS=IDRS

Hence we have

VD=VDS+VS=VDDVRD

VOLTAGE DIVIDER BIAS CONFIGURATION:

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