• The junction gate field-effect transistor (JFET or JUGFET) is the simplest type of field-effect transistor.
• They are three-terminal semiconductor devices that can be used as electronically-controlled switches, amplifiers, or voltage-controlled resistors.Unlike bipolar transistors,
• JFETs are exclusively voltage-controlled in that they do not need a biasing current. Electric charge flows through a semiconducting channel between source and drain terminals.
• By applying a reverse bias voltage to a gate terminal, the channel is "pinched", so that the electric current is impeded or switched off completely.
• A JFET is usually on when there is no potential difference between its gate and source terminals.
• If a potential difference of the proper polarity is applied between its gate and source terminals, the JFET will be more resistive to current flow, which means less current would flow in the channel between the source and drain terminals.
• Thus, JFETs are sometimes referred to as depletion-mode devices.

DIFFERENT METHODS OF BIASING IN JFET:

The general relationships that can be applied to the dc analysis of all FET amplifiers

$I_G=0;I_D=I_S$

JFET & D-MOSFET, Shockley's equation is applied to relate the input & output quantities:

$I_D=I_{DSS}(1-{ \dfrac{V_{GS}} {V_P}})^2$

For E-Type MOSFETs

: $I_ D = k( V_{GS} -V_{ T})^2$

FIXED BIAS CONFIGURATION:

The Drain Source voltage euation by applying KVL is given by

$V_{DS}=V_{DD}-I_DR_D$

We know that for when source voltage is zero that is

$V_S=0V$

$V_C=V_{DS}$

$V=V_{GS}$

$V_{GS}=-V_{GG}$

SELF BIAS CONFIGURATION:

The controlling gate-to-source voltage is now determined by the voltage across a resistor RS introduced in the source leg of the configuration 

The current through RS is the source current IS but IS = ID and

$V_{{R}_S}=I_DR_S$

By applying KVL at Gate Source junction we have

$-V_{GS}-V_{{R}_S}=0 and V_{GS}=-I_DR_S$

Substituting into Shockleys equation we have

$I_D=I_{DSS}[1-\dfrac{V_{GS}} {V_{p}}]^2$

$I_D=I_{DSS}[1+\dfrac{I_DR_{S}} {V_{p}}]^2$

Applying KVL to the output circuit to determine the VDS

$V_{{R}_S}+V_{DS}+V_{{R}_D}-V_{DD}=0$

but $I_D=I_S$

​ $V_{DS}=V_{DD}-I_D(R_S+R_D)$​

We know that $V_G=0 $ and $V_S=I_DR_S$

Hence we have

$V_D=V_{DS}+V_S=V_{DD}-V_{{R}_D}$

VOLTAGE DIVIDER BIAS CONFIGURATION: