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IC Technology Question Paper - May 19 - Electronics Engineering (Semester 7) - Mumbai University (MU)
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IC Technology - May 19
Electronics Engineering (Semester 7)
Total marks: 80
Total time: 3 Hours
INSTRUCTIONS
(1) Question 1 is compulsory.
(2) Attempt any three from the remaining questions.
(3) Draw neat diagrams wherever necessary.
Answer any Four
1.a.
Describe bonded SOI and smart cut SOI method
(5 marks)
00
1.b.
Enlist the steps for obtaining Si from sand.
(5 marks)
00
.c.
What is short channel effect? How to avoid it?
(5 marks)
00
1.d.
Explain any one application of nanowire 5
(5 marks)
00
1.e.
Explain difference between positive and negative photo resist
(5 marks)
00
2.a.
(10 marks)
00
2.b.
Explain RCA cleaning method
(5 marks)
00
2.c.
State comparison of APCVD, LPCVD and PECVD.
(5 marks)
00
3.a.
(a) Enlist step for fabrication of CMOS inverter using N well process. Draw vertical cross
sectional view starting from substrate till the gate, source and drain formation in fabrication of
CMOS inverter.
(10 marks)
00
3.b.
Draw layout of 2 input CMOS NAND gate using lambda based design rule
(10 marks)
00
4.a.
Describe with help of neat diagram of Hyness schokley experiment for measurement of
drift mobility of n type semiconductor
(10 marks)
00
4.b.
Explain Deal and Groove model for oxidation
(5 marks)
00
4.c.
Explain BiCMOS
(5 marks)
00
5.a.
What is LOCOS? Why it is required in CMOS process. Explain technology solution for
avoiding problem in LOCOS.
(10 marks)
00
5.b.
Explain Difference between schottky contact and ohmic contact
(5 marks)
00
5.c.
Explain Difference between Dry etching and Wet etching
(5 marks)
00
Write Short Notes
6.a.
MODFET devices
(4 marks)
00
6.b.
Multigate device structure
(4 marks)
00
6.c.
(4 marks)
00
6.d.
Need of lambda based design rule
(4 marks)
00
6.e.
X ray lithography
(4 marks)
00
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