Mumbai University > EXTC > Sem 3 > Analog Electronics 1

Marks: 10 M

Year: May 2014

1. Calculation for $R_{th}$ and $V_G$

Fig1 (a) determining $R_{th}$ (b) determining $V_G$

• $R_{th}=R_1||R_2$

  $=140k||60k$

  $=42kΩ$

• Calculation for $V_G$

  $V_G =\frac{V_{DD}×R_2}{R_1 +R_2}$

  $={20×60k}{140k+60k}$

  $=6V$

• The reduced circuit as shown in Fig2

Fig2 thevenin’s equivalent circuit

2. Calculation for $I_{DQ}$ and $V_{GSQ}$

$I_S=I_D+I_G$

Since $I_G≈0$

Hence $I_S≈ I_D$

• Applying KVL to gate-source node we get

  $V_G-V_{GS}-I_DR_S=0$

  $V_{GS}=V_G- I_DR_S …………..(1)$

  Now, $I_D=I_{DSS}(1-\frac{V_{GS}}{V_p} )^2 …………(2)$

• Substituting eq(1) in eq(2)

  $I_D=I_{DSS}(1-\frac{V_G - R_S ×I_D}{V_p})^2$

  $I_D=8m (1-\frac{6- 2k×I_D}{-4})^2$

• After simplification,

  $2I_D=1m (10-2kI_D)^2$

  $0=0.1-40I_D+4kI_D^2-2I_D$

• Solving above quadratic equation

  We get, $I_{D1}=3.65mA$ and $I_{D2}=6.85mA$

  • Put above two values in eq(1)

    $I_{D2}=6.85mA$ and $V_{GS2}=-7.7V$ since $| V_{GS2}|\gt|V_p|$ FET is in pinch off region and $I_D=0$ at pinch-off region.

    Hence, $I_{DQ}=I_{D1}=3.65mA$ and $V_{GSQ}=-1.3V$

3. Calculation for VDSQ

• Now, Applying KVL to drain-source channel

  $V_{DD}-V_{DS}-I_{DQ} (R_S+R_D) =0$

  $20-3.65×4.7=V_{DS}$

  $V_{DSQ}=2.845V$