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Digital Circuit Design Question Paper - Dec 17 - Electronics Engineering (Semester 3) - Mumbai University (MU)
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Digital Circuit Design - Dec 17
Electronics Engineering (Semester 3)
Total marks: 80
Total time: 3 Hours
INSTRUCTIONS
(1) Question 1 is compulsory.
(2) Attempt any three from the remaining questions.
(3) Draw neat diagrams wherever necessary.
Solve the following
1.a.
Explain the following decimals in gray code form
(5 marks)
00
1.$(42)_{10}$
2.$(17)_{10}$
1.b.
Explain characteristics of logic families.
(5 marks)
00
1.c.
State and Prove Demorgan Theorem.
(5 marks)
00
1.d.
Convert JK flip flop to T flip flop
(5 marks)
00
2.a.
What is shift register? Explain any one type of shift register.Give its applications.
(10 marks)
00
2.b.
Implement the following Boolean function using 8:1 multiplexer.
$F(A,B,C,D) =\sum M(0,1,4,5,6,8,10,12,13)$
(10 marks)
00
3.a.
Explain the Johnson's Counter.Design for initial state 0110.From initial state explain and draw all possible states.
(10 marks)
00
3.b.
Minimize the following expression using Quine McClusky technique.
$F(A,B,C,D)=\sum M(0,1,2,3,5,7,9,11)$
(10 marks)
00
4.a.
Design a 2 bit comparator and implement using logic gates.
(10 marks)
00
4.b.
Using Boolean Algebra and De-Morgan's theorem prove that
$\bar Y \bar Z+ \bar W \bar X\bar Z+\bar WXY\bar Z+WY \bar Z=Z$
(10 marks)
00
Simplify the expression $[ A \bar B(C+BD)+\bar A \bar B]C$ as much as possible.
5.a.
Explain the working of 3 bit asynchronous counter with proper timing diagram.
(10 marks)
00
5.b.
Design BCD Adder using the integrated circuit 4 bit binary adders.
(10 marks)
00
6.a.
Short note on Hazards
(5 marks)
00
6.b.
Short note on Hamming Code
(5 marks)
00
6.c.
Short note on Encoder and Decoder
(5 marks)
00
6.d.
Short note on Compare TTL and CMOS logic families
(5 marks)
00
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