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Digital Circuit Design Question Paper - May 18 - Electronics Engineering (Semester 3) - Mumbai University (MU)
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faizanshaikh
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Digital Circuit Design - May 18
Electronics Engineering (Semester 3)
Total marks: 80
Total time: 3 Hours
INSTRUCTIONS
(1) Question 1 is compulsory.
(2) Attempt any three from the remaining questions.
(3) Draw neat diagrams wherever necessary.
1.a.
Convert the following numbers as mentioned against them:
(5 marks)
00
(i) $(101011)_2$ convert to decimal number.
(ii) Convert $(129.625)_{10}$ Hexadecimal form.
(iii) Write $(-20)_{10}$ in Two's complement form.
1.b.
Write differences between synchronous and asynchronous counters.
(5 marks)
00
1.c.
Explain use of latch as a switch debouncer.
(5 marks)
00
1.d.
Explain current and voltage parameters of logic families.
(5 marks)
00
2.a.
Simplify using Quine McCluskey method and draw the logic diagram using basic gates for the following function.
(10 marks)
00
$Y = F(A,B,C,D) =\sum m(5,11,13,14,15)+\sum d(4,6,7)$
2.b.
Draw four bit Ring counter and explain its operation.
(10 marks)
00
3.a.
Implement the following function using only one 4:1 multiplexer and gates:
$Y = F(A,B,C,D) = \sum m(2,3,5,7,10,11,12,13)$
(10 marks)
00
3.b.
Design 3 bit look ahaead carry generator circuit.
(10 marks)
00
4.a.
Draw circuit diagram of 2 input TTL NAND gate and explain its operation.
(10 marks)
00
4.b.
Implement full adder using decoder having active low outputs and gates with fan in 2.
(10 marks)
00
5.a.
Design lockout free mod 10 up synchronous counter using JKMS flip flops.
(10 marks)
00
5.b.
Explain parity circuits.
(10 marks)
00
6.a.
Convert the flip flop
(10 marks)
00
(i) JKMS to D flip flop
(ii) SR to T flip flop.
6.b.
Design 8 bit comparator using 4 bit comparator IC 7485 and explain its operation.
(10 marks)
00
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