Digital Circuit Design Question Paper - Dec 18 - Electronics Engineering (Semester 3)

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faizanshaikh • 0

Digital Circuit Design - Dec 18

Electronics Engineering (Semester 3)

Total marks: 80
Total time: 3 Hours INSTRUCTIONS
(1) Question 1 is compulsory.
(2) Attempt any three from the remaining questions.
(3) Draw neat diagrams wherever necessary.

1.a. Design and implement full subtractor using logic gates.

(5 marks) 00

1.b. Explain the working of a two -inputs CMOS NOR gate with a neat Diagram.

(5 marks) 00

1.c. Design a circuit using 2:1 MUX to implement 2 input NAND Gate.

(5 marks) 00

1.d. Evaluate following operation in BCD.

(i) $(56)_{10}+(23)_{10}$ (ii) $(48)_{10}+(26)_{10}$

(5 marks) 00

2.a. Convert $(27)_{10}\ and \ (42)_{10}$

(10 marks) 00

2.b. Draw a neat circuit diagram of four bit Twisted ring counter with initial state 0000 and relevant output waveforms.

(10 marks) 00

3.a. Design a combinational logic circuit with four input variables that will produce logic 1 output when input is greater than 9.

(10 marks) 00

3.b. Draw a circuit diagram of clocked J-K flip flop using NAND gates with truth table.What is race around condition and how does it get eliminated ?

(10 marks) 00

4.a. Simplify the expression in POS form for given function and realize it with basic gates.$F(A,B,C,D)=\sum m(0,4,6,7,10,12,14)+d(2,13)$

(10 marks) 00

4.b. Convert the followings (i) SR flip flop to JK flip-flop (ii) JK flip-flop to D flip-flop.

(10 marks) 00

5.a. Implement the following expression using a single 8:1 multiplexer $F(A,B,C,D)=\sum m(0,2,4,6,8,10,12,14$)

(10 marks) 00

5.b. Simplify the following four variable Boolean function using Quine-Mccluskey technique. $F(A,B,C,D)=\sum m(0,2,3,6,7,8,10,12,13)$

(10 marks) 00

6.a. Design a Mod-5 synchronous up counter using T flip-flop.Design using minimal cost approach.

(10 marks) 00

6.b. Explain interfacing of a TTL gate driving CMOS gates and vice versa.

(10 marks) 00

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