To design fast operating parallel adder, we can use gates with lower propagation delay time, even with this approach the delay time of adder will increase with increasing number of bits to be added, another approach most commonly used is the concept of look ahead carry, it requires additional but speed of adders become independent of number of bits and it has the advantage that all the bits of the 2 numbers can be added simultaneously.

It makes operation faster.

But here, the carry required at each bit position needs, to be predicted first and this can be done as follows:

$A \rightarrow A_3 A_2 A_1 A_0$ , $B \rightarrow B_3 B_2 B_1 B_0$

$C_in \rightarrow$ carry i/p , $S \rightarrow$ SUM

$C \rightarrow$ carry generated.

At any stage the current carry produced $C_{in}$ is

$c_i = A_i B_i + A_{icm} + R_i C_{in}$

$g_i = A_i B_i \rightarrow$ carry to be generated by current addition.

$p_i = A_i + B_i \rightarrow$ carry to be propagates to the next stage.

Calculate the value of $c_a, c_1, c_2, c_g$ using given form

$C_in = g_i + p_i c_i + 1$

$i = 0 \ c_0 = g_0 + p_o c_{in}$

$i = 1 \ c_1 = g_1 + p_1 c_o = g_1 + p_1 (g_o + p_o c_{in})$

$i = 2 \ c_2 = g_2 + p_2 c_1 = g_2 + p_2 (g_1 + p_1 (g_0 + p_0 c_{in} )$

$i = 3 \ c_3 = g_3 + p_3 c_2 = g_3 + p_3 (g_2 + p_2 (g_1 + p_1 (g_0 + p_0 c_{in})$

As we can see all 4 carry required to perform the operation can be call be calculated before hand and then all 4 bits can be added together.