VHDL stand for VHSIC (Very high speed integrated circuits) Hardware description language.

1] It has now become one of electronics industry's standard language used to describe digital system.

2] con currency.

3] supports sequential statements.

4] supports for test and simulation.

5] strongly typed language.

6] supports for vendor defined libraries.

7] supports multi valued logic.

Modelling types: When a digital circuit is to be designed it is required to be described in VHDL for this we must specify an entity and an architecture at the top level and also specify an entity and architecture for each of the component modules that are part of the circuit.

There are three types of VHDL modelling

1] Structural modelling.

2] Data flow modelling.

3] Behavioral modelling.

Structural modelling.

In Structural, an entity is described as a set of interconnected components in the architecture body.

In this for each component, component instantiation statement is required in the statement part. this requires port map i.e. input and output ports to be specified, a component instantiation statement is concurrent statement, therefore statement can appear in any order, the structural modeling describes only interconnection of components without specifying behavior of the components or the entity they collectively represent.

Data flow modelling.

In this modelling, the flow of data through the entity is expressed using concurrent signal assignment statement as the name implies, the statements contained in the model assign values to signals, these statements execute concurrently i.e. in parallel not serially as in the case of programming language, the structure of the entity is not explicitly specified in this modelling, but it can be implicitly deduced.

Behavioral modelling.

In this type of modelling, the behavior of an entity is expressed using statements which are executed sequentially similar to that of high level programming language, a process statement is the main mechanism used to model the behavior of an entity, the functionality of an entity is described in an algorithmic representation in the proven statement.

The process statement starts with keyboard process and ends with the keyword GND process, a VHDL process statement can be used anywhere along with concurrent statement, Its execution is in parallel with other concurrent statements and other process.

Statements in a process are sequentially evaluated, any assignments made to the signals inside the process are not visible outside the process until all of the statements in the process have been evaluated. The process statement consist of three parts: sensitivity list, declarative part and statement part.