Successive Approximation ADC –

• A successive approximation A/D converter consists of a comparator, a successive approximation register (SAR), output latches, and a D/A converter.

• The main part of the circuit is the 8-bit SAR, whose output is given to an 8-bit D/A converter. The analog output V_a of the D/A converter is then compared to an analog signal Vin by the comparator. The output of the comparator is a serial data input to the SAR. Till the digital output (8 bits) of the SAR is equivalent to the analog input Vin, the SAR adjusts itself. The 8-bit latch at the end of conversation holds onto the resultant digital data output.

Working -

• At the start of a conversion cycle, the SAR is reset by making the start signal (S) high. The MSB of the SAR (Q7) is set as soon as the first transition from LOW to HIGH is introduced.

• The output is given to the D/A converter which produces an analog equivalent of the MSB and is compared with the analog input Vin.

• If comparator output is LOW, D/A output will be greater than Vin and the MSB will be cleared by the SAR.

• If comparator output is HIGH, D/A output will be less than Vin and the MSB will be set to the next position (Q7 to Q6) by the SAR.

According to the comparator output, the SAR will either keep or reset the Q6 bit. This process goes on until all the bits are tried. After Q0 is tried, the SAR makes the conversion complete (CC) signal HIGH to show that the parallel output lines contain valid data. The CC signal in turn enables the latch, and digital data appear at the output of the latch. As the SAR determines each bit, digital data is also available serially. As shown in the figure above, the CC signal is connected to the start conversion input in order to convert the cycle continuously. The biggest advantage of such a circuit is its high speed. It may be more complex than other A/D converters, but it offers better resolution.

Flash type ADC –

Also called the parallel A/D converter, this circuit is the simplest to understand. It is formed of a series of comparators, each one comparing the input signal to a unique reference voltage. The comparator outputs connect to the inputs of a priority encoder circuit, which then produces a binary output. The following illustration shows a N-bit flash ADC circuit:

$V_ref$ is a stable reference voltage provided by a precision voltage regulator as part of the converter circuit. As the analog input voltage exceeds the reference voltage at each comparator, the comparator outputs will sequentially saturate to a high state. The priority encoder generates a binary number based on the highest-order active input, ignoring all other active inputs. When operated, the flash ADC produces an output that looks something like this:

Even though SAR ADCs have the ability for high speed conversion, Flash type ADCs are faster and less complex, but less accurate.