In VHDL an entity is used to describe a hardware module. It is external view of the ckt we make. e.g. of entity are logic gates, multiplexers. It specifies the name of entity and interface ports. Ports are signals or terminals to communicate with other devices. At least one architecture should be there with entity. Architecture gives internal description of the design entity – its behavior, its structure or mixer of both.

Each entity is declared uniquely and it describes the following

a) Number of ports

b) Direction of ports

c) Types of ports

d) Timing information

Syntax of entity declaration

ENTITY entity name IS

PORT (port name : Signal mode IN/OUT/INOUT

Signal type : Bit, std)

END entity name.

ENTITY, IS, PORT, IN, OUT, END: Keywords.

e.g. Entity Declaration of half adder

Sum = A + B

Carry = A . B

Entity halt adder is

Port

(A : in bit ;

B : in bit ;

Sum : out bit ;

Carry : out bit)

End half adder ;