Standard Cell ASIC

Standard cell is an ASIC type that reduces physical implementation NRE cost and manufacturing time compared to full custom ICs. Standard cell ASICs, use a collection of previously layed out gates or pieces of logic called cells that must be instantiated and connected with wires to implement a circuit.

A cell might be a 2-input AND gate, a 2x1 mux or a combination of gates like two 2-input AND gates connected to an OR gate connected to an inverter. All cells are typically the same standard height, meaning they occupy the same vertical space in figure (c), so cells can be placed in standard height rows on a chip. A standard cell ASIC company pre-designs the layout for each cell, resulting in a collection or library of cell designs. The seat belt warning light circuit in figure (a) can be implemented as a standard cell ASIC by choosing appropriate cells from cell library as in figure (b), instantiating and wiring those cells as in figure (c) and fabricating an IC as in figure (d).

A typical cell library might contain hundreds or thousands of cells, the cell library shown in figure (b), having just five cells, is trivially small and for illustrative purposes only. A typical standard cell ASIC may have millions of cells not just a few as in the figure.

Gate Arrays (Structured ASICs)

A standard cell ASIC, while having lower NRE and involving less time than full-custom ICs, must still have all its layers fabricated. A gate array ASIC involves a chip whose transistors are predesigned to form rows of logic gates on the chip, as shown in figure (b), meaning that only the wires remain to be fabricated. Creating the wires represents just the last steps of fabrication and thus gate array technology eliminates much of the time and cost of fabricating a chip for a particular circuit.

A gate array company predesigns and mass produces the gate array chip. When a client wants a circuit on an IC, the company then customizes some of those chips for the client's circuit by fabricating the metal layers. Figure illustrates how the seat belt warning light desired circuit in figure (a) might be implemented using the gate array chip in figure (b) consisting of a row of 2 input AND gates, a row of 2-input OR gates and a row of inverters. Figure (c) shows how to map the desired circuit's 3 input AND gate using two of the gate array's available 2 input AND gates and how to map the desired inverter to one of the gate array inverters.

The figure also shows how the desired wiring among the gate array' pins, the gate array AND gate and the gate array inverter might be implemented. The remaining gates and pins on the gate array chip would be unutilized. fabricating those wires would result in the IC being customized to the seat belt application in figure (d).