RTL design follows a two step process, as was the case for combinational and sequential designs. The first step is to capture the desired behavior and the second step is to convert that behavior as a circuit. Converting an HLSM to a circuit is aided by the use of a standard processor architecture, similar to how converting an FSM to a circuit was aided by the use of a standard controller architecture consisting of a state register and combinational logic. A standard processor architecture is shown consisting of a controller connected with a datapath.

The datapath will have the ability to carry out each particular data operation present in the HLSM, by having the necessary datapath components. The controller will set the control input signals of the various datapath components to carry out the specific actions of each particular state and to transition to appropriate next states based on the control output signals of those datapath components.

To help understand the controller/datapath pair in the standard processor architecture, consider the cycles high counter which is revisited in figure. Figure (a) shows the system block diagram and describes the system's desired behavior. As the convention is to always register data outputs, the figure already shows a register $P_{reg}$ connected to data output P. Figure (b) shows the desired behavior captured as an HLSM created. The behavior requires that the computation "$P_{reg} = P_{reg} + 1$" be performed. As such, figure (c) shows an adder whose two inputs are $P_{reg}$ and a constant 1, and whose output is connected to $P_{reg}$. Thus, computing "P_{reg} = P_{reg} + 1" can be achieved simply by setting $P_{reg}$'s 1d control input to 1. Furthermore, the required computation "P_{reg} = 0" can be achieved by setting $P_{reg}$'s clr control input to 1. Thus, the circuit of the adder and register form a datapath that is capable of performing the data computation required for the system's behavior.

In the figure, to control that datapath to carry out the right computation at the right time to achieve the desired cycles high count behavior. That component is a controller as shown in figure (d). The controller's behavior is described as an FSM and is similar to the HLSM's behavior in Figure (b), except that each desired data operation is replaced by control actions that use the datapath to carry out the desired data operatrion. Rather than "$P_{reg} = 0$", the controller's FSM executes the action "P_{reg} _clr = 1" which clears the register.

Rather than "$P_{reg}$ = P_{reg} + 1", the controller's FSM executes the action "Preg_1d = 1", which loads Preg with Preg +1 because that is how the datapath is set up. The controller thus uses the datapath to implement the overall desired system behavior. The FSM in figure (d) could be converted to a circuit, thus completing the design of the cycle-high count processor circuit.

As seen in the figure, converting an HLSM to a controller and datapath circuit requires creating a datapath capable of carrying out the required data operation, connecting the datapath to a controller block and converting the HLSM into an FSM that describes the controller's behavior.