Circuit Realization using pass transistor logic:

1. $2^n:1$ MUX using pass transistor,

1. Implement 2 : 4 decoder using pass transistor logic,

D- Flip-Flop using Pass transistor:-

Master- slave D-F/F:-

Transmission Gate logic:-

nMOS $V_{DSn} = V_{DD} - V_{out}$

$V_{GSn} = V_{DD} - V_{out}$

nMOS will turn-off when $V_{out} \gt V_{DD} - V_{TD}$

nMOS will remain in saturation for $V_{out} \lt V_{DD} - V_{TD}$

pMOS $V_{OSp} = V_{out} - V_{DD}$

$V_{GSn} = -V_{DD}$

pMOS in saturation for $V_{out} \lt |V_{Tp}|$

& in linear for $V_{out} \gt |V_{Tp}|$

A -> B When A = 0 through nMOS

A -> B When A = 1 through pMOS

$I_D = I_{DSp} + I_{DSn}$

C = 1 = $V_{DD}$ Both transistors ON-Low Reg path

c = 0 -> Both OFF -> High Impedence

OR Gate:

AND Gate:

XOR Gate:

XNOR Gate:

NAND Gate:

NOR Gate: