Pseudo nMOS logic:

Rationed Logic:

$V_{OL} = \frac{K_P(V_{DD} + V_{TP})V_{DSatP}}{K_n(V_{DD} - V_{Th})} = \frac{\mu_p w_p}{\mu_n W_n}V_{DsatP}$

1) $V_{OH} = V_{DD}$

$V_{OL} != 0$

2) Static Power Dissipation is significant.

3) Since the voltage swing on the output & over functinality of the gate depend on ratio of nMOS & pMOS transistor sizes, these cKt is called rationed ckt.

4) To get $V_{OL}$ as small as possible, the pmos should be sized it causes a negative impact on propogation delay for charging is limited.

A major disadv of pseudo nmos gate is static power that is dissipated when o/p is low through direct current path i.e. existing bet $V_{DD}$ & Gnd.

Pseudo - nMOS VTC :

Tristate cKt :

Clocked CMOS or $C^2$MOS ckts:

Drawbacks:

1) O/P note cannot hold charger for longer time. This puts limitations on allowable clock frequecy.

2) These gates have same i/p capacitance as regular complementory gates but larger rise and fall times due to series clocking transistor which can be either at the o/p of gate or at the power supply.

3) $C^2$MOS circuitory is one of the recommended remedy for HOT electron effects, because it places on n-transistor in series with logic transistor.

Q. Using clocked CMOS, draw 2 i/p NAND & NOR.

Dynamic Logic ckts:

Dynamic CMOS - 2 stages:

Dynamic CMOS logic design:

Domino CMOS logic design:

Advantages:

• Compare to static cmos.

• Single clock is used to precharge & evaluate any no of cascaded stages, as long as propogation from it stage to last stage does not exceed the time span of E-stage.

• Conventional static CMOS static gate can be used together domino. CMOS gate in cascadded config with limitation to that no of inverting static logic gates transistion during variation.

Major Limitation to this only non inverting expressions.

If necessary, inversion must be carried using conventional logic of CMOS.

• Dynamic CMOS stages driven by some clock signak cannot be caused directly. CMOS ckt like large noise margin, low power dissipation and load transistor count.

Q. Z = AB + (C + D)(E + F) + GH

Realise the logic using

i) Static CMOS Desing

ii) Domino Logic

Comment on no of transistors reqd.

Sol:- $Z|_{dual} = (A +B)(CD) + (EF)(G + H)$

Domino :

NORA logic or N-P CMOS logic:

$\phi$ = High => nMOS conducts & i/p to the next n Blosck is low i.e. it is OFF.

Hence at the begining of evaluation phase are transistors in the P & n block are OFF.

• The adv of NORA CMOS logic is that a static CMOS inv is not required at the o/p of every dynamic logic stage. Instead a direct coupling of logic block is fessible by alternating nMOS and pMOS logic box.

• NORA logic is alos compatible with domino CMOS logic.

• op's of NORA nMOS logic block can be inverter and applied to the i/p of the domino CMOS bkock which also driven by clock.

• Similarly buffered o/p of domino CMOS stage can be applied directly to the i/p of the logic.

• It allows pipeline, system architecture

Disadv of NORA logic is that it suffers from charge sharing & leakage problem.

General ckt and clock structure of Zipper.

1) Identical to NORA except clock signals.

2) Requires slightly different clock signals for the precharge transistors and for the pull down transistors.

3) Clock signals whoch drive pMOS precharge & nMOS discharge transistors allow these transistors to remain in weak conduction or near cut-off during evaluate phase, thus leakage.

Charge Sharing:

Pass Transistor logic:

i/p = $V_x = V_{DD}$

i/p = $V_x = 0$

o/p = $V_y = V_{DD}$

o/p = $V_o = |V_{TP}|$

1) NEET can only pass a weak logic '1' & strong logic '0'

2) PFET can only pass a weak logic '0' & strong '1'

Rule of (2) ensure that low impedence to the supply rail under all circumstances

Disadv : Body bias effect of (2) when A = 1, B = 0

Static CMOS => C trans.

Node voltages during logic 1 transfer, when each pass transistor drivers another pass transistor.

2 i/p NAND, when B = 0 $B_{-} = 1$ => Y = 1

B = 1 $B_{-} = 0$ => Y = $A_{-}$

2 i/p NOR, when B = 0 $B_{-} = 1$ => Y = $A^{-}$

B = 1 $B_{-} = 0$ => Y = 0