1. Static CMOS ckts

2. Pseudo CMOS ckts

3. Tristate ckts

4. Clocked CMOS or $C^2$MOS ckts

5. Dynamic CMOS logic ckts

6. Domino CMOS logic

7. Zipper CMOS logic ckts

8. Pass transistor logic

9. Transmission Gate logic

10. Nora CMOS logic

Q4] 1) Best Case switching

a) NAND

For p-network

$(W/L)_{eq} = x + x = 2W$

x = W

For n-network

$(W/L)_{eq} = x/2 = W$

x = 2W

b) NOR

For p-network

$(W/L)_{eq} = x /2 = 2W$

x = 4W

For n-network

$(W/L)_{eq} = 2x = W$

x = W/2

2) Worst case Switching:

a) NAND

For p-network

(Pull up n/w)

1) A, $(W/L)_{Aeq} = x = 2W$

x = 2W

2) B, $(W/L)_{Beq} = x = 2W$

x = 2W

pull down n/W

1) AB, $(W/L)_{ABeq} = x/2 = W$

x = 2W

b) NOR

(Pull down n/w)

1) A, $(W/L)_{Aeq} = x = W$

x = W

pull up n/W

1) AB, $(W/L)_{ABeq} = x/2 = 2W$

x = 4W

Q5] 3 - i/p NAND Gate,

$Y = (A.B.C)^{-}$

$Y^{-}|_{dual}$ = A + B + c

3-i/p XOR Gate,

$Y = A (+) B (+) C = A^{-}B^{-}C + A^{-}BC^{-} + AB^{-}C^{-} + ABC$

$Y^{-}| = (A (+) B (+) C)^{-}$