The basic building block of NORA logic is the $\phi -section$ logic network illustrated in Figure. This consists of a dynamic nMOS logic state that is cascaded into a dynamic pMOS logic gate; a $C^2MOS$ inverter is used as an output latch. Note that optional inverters are provided at the outputs of both logic gates if, for example, one wishes to use a glitch-free domino nMOS-nMOS cascade. Moreover, the ordering of the logic gates may be reversed (i.e., pMOS to nMOS) without loss of generality.

The main features of NORA logic arise from the manner in which the clocks are applied to the logic gates and the $C^2MOS$ latch. A clock value of $\phi=0$ defines the precharge interval for the $\phi-section$ the main features are shown in Figure (a). The output capacitors of the logic stages are precharged to values of

$C_1: V_1 \rightarrow V_{DD}$

$C_2: V_2 \rightarrow 0V$

for the nMOS and pMOS gates, respectively. The most important aspect of the precharge is noting that the output of the $C^2MOS$ latch is in the Hi-Z state at this time. This means that the voltage $V_{out}$ on $C_{out}$ is not affected by the precharge states. The actual value of $V_{out}$ is due to charge held on the capacitor. When the clock makes a transition to $\phi = 1$ the entire section goes into evaluation as illustrated in Figure (b). During this time, the inputs are valid and the output result from the logic chain is given by the voltage $V_{out}$ on the output capacitor $C_{out}$.This is held when the clock changes back to $\phi = 0$ for the next precharge event. The operation of the $\phi-section$ is summarized by the simplified block diagrams in Figure

Next, we construct a NORA $\phi-section$ that has the general features shown in Figure. We again use a cascade of dynamic logic gates with alternating polarities (nMOS to pMOS, etc.), and provide a $C^2MOS$ tri-state latch at the output. The only difference is that the clock phases $\phi$ and $\bar \phi$ have been reversed everywhere throughout the circuit. This means that a $\bar \phi-section$ precharges when $\phi = 1$ and undergoes evaluations when $\phi = 0$,exactly opposite to the behavior of a $\phi-section$.

The no race characteristic of the design style is obtained by creating an alternating cascade of $\phi and \bar \phi-sections$ as in Figure.

The timing of the two section types automatically ensures that signal races cannot occur through either section. To understand this comment, consider the operational drawings in Figure. When the clock is at a value $\phi = 1$ the $\phi-section$ are in evaluation and the $\bar \phi-section$ are undergoing precharge. This is shown in Figure (a). Consider the first logic section in the chain. During this time, the inputs are valid and yield results at the output. However, since the next logic group is a $\phi-section$, it is in precharge with $\phi = 1$ and does not accept input data values. This eliminates race problems through the $\bar \phi-section$.

Similarly, when the clock changes to $\phi = 0$ as in Figure (b), the $\phi-section$ are in precharge and block data transmission while the $\bar \phi-section$ undergo evaluation. As the clock oscillates, the sections take turns evaluating the inputs and blocking data transmission. The race-free characteristics remain even in the presence of clock skew, and the structuring of the logic into separate $\phi$ and $\phi-section$ is convenient for designing pipelined systems.