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MODULE 1 : UNIT 1
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SPICE Simulation

LEVEL 1 (MOS 1) -> Square law current voltage cahract

LEVEL 2 (MOS 2) -> Detailed Analytical MOSFET model

LEVEL 3 (MOS 3) -> Semhempirical model

BSIM (Berkley Short Channel Mode for IGFET)

LEVEL 2 & LEVEL 3 includes second order effects such as

i) Short Channel

ii) Subthreshold Conduction

iii) Scattering limited velocity saturation

iv) Charge controlled capacitances

The equivalent ckt structure of the NMOS level 1 model, which is the default MOSFET model is SPICE

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LEVEL 1

=> Simple model based on current voltage relation

=> GCA based Quadratic model

=> Developed in 1960 by sah

ID(lin)=K2WLeff[2(VGSVT)VDSV2DS](1+λVDS)

for VGS>VT and VDS<VGSVT

ID(sat)=K2WLeff[VGS]2(1+λVDS)

for VGS>VT and VDS>VGSVT

λ = cahnnel length

VT=VTO+ν((12ϕF+VB)1/2(12ϕF)1/2)

Leff = L - 2Ld

Electric parameters => K,VTO,λ,ν,12ϕF

Physical parameter => LD,μ,tOX,NA

K=μEOX[μA/V2]

ν=(2ESiqNA)1/2EOX[V1/2]

2ϕF=2KTqln(niNA)[V]

λ = 0 Typically

Level 2 Model

ID=IDsat1(1λVDS)

VTO=ϕGC=I.NssEOX+|2ϕF|+ν(12ϕF)1/2

Level 1:

  • Model is not very precise due to gradually channel approximation used in the derivation of model equations is too approximated And no of filling parameter

  • t so small

  • Usefull for quick and rough estimate of ckt performance without much accuracy

Level 2:

  • it support additional effect as listed above. If all the parameter in level 2 are specified by user then greatest leel of complexity will be not obtained in such cases it requires large amt of CPO time for calculation.

Level 3 :

In this we get same accuracy as lvl 2 but CPU time is significantly less and no of iteration are fewer. However disadvantage is that it leads to complexity of calculating sum of it model parameter

BSIM Model :

  • Analytical simple

  • based on small no of parameter which are normally extracted from ext data

  • one of the most popular model used in electronic industry due to accuracy & n.

  • Widely used to accurately model the electrical behaviour of submicron MOSFET that are manufactured with various submicron CMOS frabication process

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